Apparatus and Method for Hardware Initiation of Emulated Instructions

• US 20120323552A1
• Filed: 06/15/2011
• Published: 12/20/2012
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Lau, David Yiu-Man
• Granted Patent: US 10,496,461 B2
• Time in Patent Office: Days
• US Class Current: 703/26
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 2009/45591 Monitoring or debugging support
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

Claims

1. A method of emulating an instruction, comprising:

identifying a fault instruction;

saving the fault instruction in a register;

associating the fault instruction with a software emulated operation; and

initiating the software emulated operation with an access to the fault instruction in the register.

2. The method of claim 1 further comprising executing the software emulated operation to support a guest machine operation.

3. The method of claim 1 further comprising executing the software emulated operation to support a floating point unit operation.

4. The method of claim 1 further comprising executing the software emulated operation to support a new instruction on a legacy hardware resource.

5. The method of claim 1 wherein initiating includes a method call with the fault instruction as a passed parameter.

6. A machine, comprising:

a processor including a fault register to store a fault instruction; and

a memory connected to the processor, the memory including instructions executable by the processor to initiate a software emulated operation with an access to the fault instruction in the fault register.

7. The machine of claim 6 wherein the processor initiates a method call with the fault instruction as a passed parameter.

8. The machine of claim 6 further comprising a configuration register to specify the presence of the fault register.

9. The machine of claim 6 wherein the emulated operation is selected from a virtualization operation and a floating point unit operation.

10. A processor, comprising:

a fault register to store a fault instruction; and

an exception handler to invoke a software emulated operation utilizing the fault instruction from the fault register.

11. The processor of claim 10 wherein the exception handler generates a method call with the fault instruction as a passed parameter.

12. The processor of claim 10 further comprising a configuration register to specify the presence of the fault register.

13. A computer readable storage medium including executable instructions to define a processor, comprising:

a fault register to store a fault instruction; and

an exception handler to invoke a software emulated operation utilizing the fault instruction from the fault register.

14. The computer readable storage medium of claim 13 wherein the exception handler generates a method call with the fault instruction as a passed parameter.

15. The computer readable storage medium of claim 13 further comprising a configuration register to specify the presence of the fault register.