METHODS AND APPARATUS FOR DATA ACCESS BY A REPROGRAMMABLE CIRCUIT MODULE

• US 20120324143A1
• Filed: 06/15/2011
• Published: 12/20/2012
• Est. Priority Date: 06/15/2011
• Status: Abandoned Application

• Current Assignee: Data Design Corporation
• Original Assignee: Data Design Corporation
• Inventors: Giganti, John J., Huo, Andrew, Baum, Richard A., Cavallo, John M.
• Application Number:
  US13/161,141
• Publication Number:
  US 20120324143A1
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

In some embodiments, an apparatus includes a set of memory modules, a reprogrammable circuit module and a set of data channels. Each memory module is associated with an address translation table configured to store a set of address pairs each including a physical memory address and a logical memory address. The reprogrammable circuit module is configured to retrieve a first physical memory address associated with a first logical memory address and a second physical memory address associated with a second logical memory address. Each data channel couples the reprogrammable circuit module to at least one memory module. The reprogrammable circuit module is configured to send a first and a second query to the first and the second memory module, via a first data channel based on the first physical memory address or a second data channel based on the second physical memory address, respectively.

Claims

1. An apparatus, comprising:

a plurality of memory modules, each memory module from the plurality of memory modules being associated with an address translation table configured to store a plurality of address pairs, each address pair from the plurality of address pairs including (1) a physical memory address associated with a physical location in a memory module from the plurality of memory modules and (2) a logical memory address associated with the physical memory address;

a reprogrammable circuit module configured to execute a search process based at least in part on data stored at the plurality of memory modules, the search process configured to retrieve a first physical memory address associated with a first logical memory address from an address translation table associated with a first memory module from the plurality of memory modules and a second physical memory address associated with a second logical memory address from an address translation table associated with a second memory module from the plurality of memory modules; and

a plurality of data channels, each data channel from the plurality of data channels operably coupling the reprogrammable circuit module to at least one memory module from the plurality of memory modules, the reprogrammable circuit module configured to send, based on the search process, a first query to the first memory module via a first data channel from the plurality of data channels based on the first physical memory address and a second query to the second memory module via a second data channel from the plurality of data channels based on the second memory address.

2. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is included in a dual in-line memory module (DIMM).

3. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to randomly associate the first physical memory address with the first logical memory address.

4. The apparatus of claim 1, wherein the first logical memory address is adjacent to the second logical memory address, the first physical memory address not adjacent to the second physical memory address.

5. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to send the first query at substantially a same time as the second query.

6. The apparatus of claim 1, wherein the reprogrammable circuit module is a Field Programmable Gate Array (FPGA).

7. The apparatus of claim 1, wherein each memory module from the plurality of memory modules is a flash memory module.

8. The apparatus of claim 1, wherein the reprogrammable circuit module is configured to be modified by a driver module.

9. The apparatus of claim 1, wherein the plurality of memory modules are removably coupled to a Peripheral Component Interconnect Express (PCIe) card including the reprogrammable circuit module.

10. A method, comprising:

receiving a query associated with a data lookup, the query including a first logical memory address and a second logical memory address;

retrieving a first physical memory address associated with the first logical memory address, the first physical memory address being associated with a memory location at a first memory module coupled to a reprogrammable circuit module by a first data channel;

retrieving a second physical memory address associated with the second logical memory address, the second physical memory address being associated with a memory location at a second memory module coupled to the reprogrammable circuit module by a second data channel;

accessing, during a first time period, the first memory module via the first data channel using the first physical memory address; and

accessing, at a second time period overlapping the first time period, the second memory module via the second data channel using the second physical memory address.

11. The method of claim 10, wherein the retrieving the first physical memory address includes retrieving the first physical memory address from a first address translation table, the retrieving the second physical memory address includes retrieving the second physical memory address from a second address translation table.

12. The method of claim 10, wherein the retrieving the first physical memory address includes retrieving the first physical memory address from an address translation table stored at the first memory module.

13. The method of claim 10, wherein the first memory module is included within a common dual in-line memory module (DIMM) as the second memory module.

14. The apparatus of claim 10, wherein the first memory module is a flash memory module.

15. The method of claim 10, wherein the accessing the first memory module and the accessing the second memory module are associated with a search process, the method further comprising:

receiving an instruction from a driver associated with the reprogrammable circuit module to modify the search process.

16. An apparatus, comprising:

a first reprogrammable circuit module; and

a memory package including a plurality of memory modules, the memory package being removably coupled to the first reprogrammable circuit module such that the memory package is physically coupled to the first reprogrammable circuit module when in a first configuration and physically coupled to a second reprogrammable circuit module when in a second configuration,

the memory package being operatively coupled to the first reprogrammable circuit module via a plurality of channels when in the first configuration,

at least one memory module from the plurality of memory modules configured to store an address translation table having a plurality of address pairs associated with the plurality of memory modules, each address pair from the plurality of address pairs including (1) a physical memory address associated with a physical location in the plurality of memory modules and (2) a logical memory address associated with the physical memory address,

the first reprogrammable circuit module configured to use the plurality of address pairs to execute a search process via the plurality of channels after the memory package is moved from the second configuration to the first configuration, wherein the search process is substantially the same as a search process executed by the second reprogrammable circuit module when the memory package is in the second configuration.

17. The apparatus of claim 16, wherein the memory package is a dual in-line memory module (DIMM), each memory module from the plurality of memory modules being a flash memory module.

18. The apparatus of claim 16, wherein the first reprogrammable circuit module is a Field Programmable Gate Array (FPGA).

19. The apparatus of claim 16, wherein the search process executed by the first reprogrammable circuit module is configured to retrieve a physical memory address associated with a received logical memory address using the address translation table.

20. The apparatus of claim 16, wherein the first reprogrammable circuit module is configured to send a first query to a first memory module from the plurality of memory modules during a first time period, the first reprogrammable circuit module configured to send a second query to a second memory module from the plurality of memory modules during a second time period overlapping the first time period.