MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS
First Claim
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1. A memory controller, comprising:
- a plurality of back end channels; and
a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of write commands,wherein the command dispatcher is configured to determine a net change to memory to be accomplished by the number of write commands, and to modify one or more of the number of write commands in order to optimize distribution of the number of write commands among the plurality of back end channels.
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Abstract
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
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Citations
20 Claims
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1. A memory controller, comprising:
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a plurality of back end channels; and a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of write commands, wherein the command dispatcher is configured to determine a net change to memory to be accomplished by the number of write commands, and to modify one or more of the number of write commands in order to optimize distribution of the number of write commands among the plurality of back end channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A memory controller, comprising:
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a plurality of back end channels; and a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of write commands, wherein the command dispatcher is configured to determine a net write to memory to be accomplished by the number of write commands, and to provide write commands to accomplish the net write among the plurality of back end channels using fewer than the number of write commands. - View Dependent Claims (18, 19)
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20. A memory controller, comprising:
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a plurality of back end channels, each back end channel corresponding to a different memory device; a command queue configured to hold a number of write commands; and a front end command dispatcher communicatively coupled to the plurality of back end channels and the command queue, wherein the command dispatcher includes a command processor portion configured to determine a net write to memory to be accomplished by the number of write commands, and to delete and/or modify one or more of the number of write commands in order to reduce a quantity of write commands distributed among the plurality of back end channels.
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Specification