INTELLIGENT BIT RECOVERY FOR FLASH MEMORY

• US 20120324276A1
• Filed: 10/31/2011
• Published: 12/20/2012
• Est. Priority Date: 06/19/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Frayer, Jack Edward, Olbrich, Aaron Keith, Kulkarni, Anand Krishnamurthi, Stonelake, Paul Roger, Ma, Yale Yueh
• Granted Patent: US 8,910,020 B2
• Time in Patent Office: Days
• US Class Current: 714/6.11
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

Claims

1. A method of recovery of bits in a flash memory device, the method comprising:

in the flash memory device with a controller;

determining N bits of data for recovery;

selecting, based on at least one aspect of the flash memory device, potential bit patterns of the N bits, the potential bit patterns being smaller in number than 2^N; and

iteratively determining whether the potential bit patterns enable recovery of at least some of the N bits.

2. The method of claim 1, wherein the N bits of data for recovery are determined by reading the N bits of data to determine whether the N bits are toggling.

3. The method of claim 1, wherein selecting the potential bit patterns is by identifying one of more potential problems.

4. The method of claim 3, wherein identifying the one or more potential problems includes analyzing test bits to identify one of over-programming or loss retention.

5. The method of claim 1, wherein the potential bit patterns are selected based on a type of at least a part of the flash memory device.

6. The method of claim 5, wherein the potential bit patterns are selected based on whether the N bits of data for recovery are in single level cells or multi-level cells.

7. The method of claim 1, wherein the potential bit patterns are selected based on values of the N bits of data for recovery.

8. The method of claim 1, wherein the potential bit patterns are selected independent of values of the N bits of data for recovery.

9. The method of claim 1, wherein the flash memory device includes multi-level cells;

and

wherein the N bits for recovery are in a page under recovery; and

wherein the potential bit patterns are selected based on which bit in the multi-level cell is subject to recovery.

10. The method of claim 9, wherein the multi-level cells comprise 2-bit multi-level cells with an upper page and a lower page;

wherein the page under recovery is the upper page;

wherein the paired page is the lower page; and

wherein the potential bit patterns are selected based on values of bits in the lower page.

11. The method of claim 1, wherein iteratively determining whether the potential bit patterns enable recovery of at least some of the N bits comprises analyzing the potential bit patterns with error correction coding.

12. A method of recovery of bits in a flash memory device caused by one or more potential flash memory problems, the method comprising:

in the flash memory device with a controller;

determining N bits of data for recovery;

selecting potential bit patterns of the N bits, the potential bit patterns for correction of the one or more potential flash memory problems and being smaller in number than 2^N; and

iteratively determining whether the potential bit patterns enable recovery of at least some of the N bits.

13. The method of claim 12, wherein the potential bit patterns are selected for correction of one or both of over-programming and retention loss.

14. The method of claim 12, wherein determining N bits of data for recovery comprises determining that the N bits of data are toggling.

15. The method of claim 14, further comprising determining that M bits of data are further in error;

and

wherein iteratively determining whether the potential bit patterns enable recovery of at least some of the N bits comprises determining whether one of the potential bit patterns recovers a sufficient number of bits to correct for N+M error bits.

16. A flash memory device comprising

a memory;

and

a controller in communication with the memory, the controller configured to;

determine N bits of data for recovery in the memory;

select, based on at least one aspect of the flash memory device, potential bit patterns of the N bits, the potential bit patterns being smaller in number than 2^N; and

iteratively determine whether the potential bit patterns enable recovery of at least some of the N bits.

17. The flash memory device of claim 16, wherein the controller is configured to determine the N bits of data for recovery by reading the N bits of data to determine whether the N bits are toggling.

18. The flash memory device of claim 16, wherein the controller is configured to select the potential bit patterns by identifying one of more potential problems.

19. The flash memory device of claim 18, wherein the controller is configured to identify the one or more potential problems by analyzing test bits to identify one of over-programming or loss retention.

20. The flash memory device of claim 16, wherein the controller is configured to select the potential bit patterns based on a type of at least a part of the flash memory device.

21. The flash memory device of claim 20, wherein the controller is configured to select the potential bit patterns based on whether the N bits of data for recovery are in a single level cells or multi-level cells.

22. The flash memory device of claim 16, wherein the controller is configured to select the potential bit patterns based on values of the N bits of data for recovery.

23. The flash memory device of claim 16, wherein the controller is configured to select the potential bit patterns independent of values of the N bits of data for recovery.

24. The flash memory device of claim 16, wherein the memory includes multi-level cells;

and

wherein the N bits for recovery are in a page under recovery; and

wherein the controller is configured to select the potential bit patterns based on which bit in the multi-level cell is subject to recovery.

25. The flash memory device of claim 24, wherein the multi-level cells comprise 2-bit multi-level cells with an upper page and a lower page;

wherein the page under recovery is the upper page;

wherein the paired page is the lower page; and

wherein the controller is configured to select the potential bit patterns based on values of bits in the lower page.

26. The flash memory device of claim 16, wherein the controller is configured to iteratively determine whether the potential bit patterns enable recovery of at least some of the N bits by analyzing the potential bit patterns with error correction coding.

27. A flash memory device comprising

a memory;

and

a controller in communication with the memory, the controller configured to;

determine N bits of data for recovery;

select potential bit patterns of the N bits, the potential bit patterns for correction of the one or more potential flash memory problems and being smaller in number than 2^N; and

iteratively determine whether the potential bit patterns enable recovery of at least some of the N bits.

28. The flash memory device of claim 27, wherein the controller is configured to select the potential bit patterns for correction of one or both of over-programming and retention loss.

29. The flash memory device of claim 27, wherein the controller is configured to determine N bits of data for recovery by determining that the N bits of data are toggling.

30. The flash memory device of claim 29, wherein the controller is further configured to determine that M bits of data are further in error;

and

wherein the controller is configured to iteratively determine whether the potential bit patterns enable recovery of at least some of the N bits by determining whether one of the potential bit patterns recovers a sufficient number of bits to correct for N+M error bits.