6F2 DRAM Cell
First Claim
Patent Images
1. A DRAM array comprising:
- a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line, the other source/drain region of each access transistor being separated from other source/drain regions of access transistors of adjacent pairs of cells by common channel regions defined by the n-type source/drain regions;
access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and
dummy word lines extending generally perpendicular to the bit line, each dummy word line extending over one of the common channel regions, the dummy word lines comprise a material with a work function favoring p-channel devices.
2 Assignments
0 Petitions
Accused Products
Abstract
A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
-
Citations
24 Claims
-
1. A DRAM array comprising:
-
a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line, the other source/drain region of each access transistor being separated from other source/drain regions of access transistors of adjacent pairs of cells by common channel regions defined by the n-type source/drain regions; access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and dummy word lines extending generally perpendicular to the bit line, each dummy word line extending over one of the common channel regions, the dummy word lines comprise a material with a work function favoring p-channel devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A DRAM array comprising:
-
a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line; access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and wherein the channel regions of the access transistors are angled with respect to their source/drain regions. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
-
-
20. A DRAM array comprising:
-
a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line; access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and wherein the word lines are maintained at a negative potential with respect to a substrate potential when the access word line is deselected. - View Dependent Claims (21, 22, 23, 24)
-
Specification