METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20120326227A1
• Filed: 06/27/2011
• Published: 12/27/2012
• Est. Priority Date: 06/27/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Burke, Peter A., Grivna, Gordon M., Padmanabhan, Balaji, Venkatraman, Prasad
• Granted Patent: US 8,889,532 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Claims

1. A method for forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a trench extending from the major surface;

forming a first layer overlying surfaces of the trench;

forming a spacer layer adjacent the first layer, where the spacer layer comprises a material different than the first layer;

forming a first region comprising a material different than the spacer layer in proximity to a lower surface of the trench;

forming a first electrode in a lower portion of the trench and adjacent portions of the spacer layer and the first region, where portions of the first layer are between the first electrode and the region of semiconductor material;

forming a dielectric layer above the first electrode; and

forming a second electrode adjacent the first layer and the dielectric layer, where at least a portion of the second electrode is within the trench.

2. The method of claim 1 further comprising the steps of:

forming a body region adjoining the trench; and

forming a source region adjoining the body region and the trench, where the step of forming the first layer comprises forming a gate dielectric layer, and where the step of forming the first electrode includes forming a shield electrode, and where the step of forming the second electrode includes forming a gate electrode.

3. The method of claim 1, where the step of forming the spacer layer includes the steps of:

forming a third layer adjacent the first layer; and

removing a portion of the third layer in proximity to the lower surface of the trench.

4. The method of claim 3 further comprising the steps of forming a non-conformal layer overlying the major surface and adjacent the third layer before the step of removing a portion of the third layer, and where the non-conformal layer is thicker in proximity to upper surfaces of the trench.

5. The method of claim 1 further comprising the step of removing portions of the first layer underlying the spacer layer before the step of forming the first region.

6. The method of claim 1, where the step of forming the first layer includes forming a first layer comprising silicon oxide, and where the step of forming the first region includes forming the first region comprising silicon oxide.

7. The method of claim 6, where the step of forming the spacer layer comprises forming the spacer layer comprising silicon nitride.

8. The method of claim 1 further comprising the step of forming a polycrystalline semiconductor spacer layer adjacent the spacer layer before the step of forming the first region.

9. The method of claim 1, where the step of forming the source region comprises forming a source region having an extension portion adjoining the trench and a central portion adjoining the extension portion, where the central portion is shallower than the extension portion.

10. The method of claim 1, where the step of forming the first region includes forming the first region having a thickness that increases along lower sidewall surfaces of the trench, where the thickness is greatest in proximity to a lowest portion of the trench.

11. The method of claim 1, where the step of forming the first electrode includes forming the first electrode having a stepped shape.

12. A method for forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a trench extending from the major surface, where the trench has sidewall surfaces and a lower surface;

forming a first dielectric layer adjoining the sidewall surfaces and the lower surfaces;

forming first spacer layers adjacent the gate dielectric layer while leaving a segment of the gate dielectric layer exposed in proximity to the lower surface;

removing portions of the first dielectric layer from the lower surface adjacent the first spacer layers and the region of semiconductor material;

forming a first dielectric region adjoining the lower surface, where the first dielectric layer is thicker than the gate dielectric layer;

forming a second dielectric layer adjacent the spacer layers;

forming a first conductive region adjacent the first dielectric region and the second dielectric layer;

forming a second dielectric region adjacent an upper surface of the first electrode;

removing portions of the second dielectric layer and spacer layers adjacent upper portions of the trench; and

forming a second conductive region adjacent the first dielectric layer and the second dielectric region.

13. The method of claim 12, where the step of forming the first spacer layers comprises the steps of:

forming a layer of material adjacent the first dielectric layer;

forming a non-conformal layer of material adjacent the layer of material, where the non-conformal layer is thicker in proximity to upper portions of the trench; and

removing portions of the non-conformal layer and the layer of material in proximity to the lower surface.

14. The method of claim 13, where the step of forming the layer of material comprises forming a silicon nitride layer having a thickness of about 0.01 microns to about 0.05 microns, and where step of forming the non-conformal layer of material comprises depositing a silicon oxide using PECVD with a silane source gas.

15. The method of claim 12, where the step of forming the first spacer layers comprises the steps of:

forming a layer of material adjacent the first dielectric layer;

forming polycrystalline semiconductor spacers adjacent the layer of material; and

removing portions of the layer of material in proximity to the lower surface.

16. The method of claim 12, where the step of removing portions of the first dielectric layer from the lower surface adjacent the first spacer layers and the region of semiconductor material comprises removing portions of the first dielectric layer adjacent lower sidewall surfaces of the trench to form undercut portions, and where the step of forming the first dielectric region comprises forming the first dielectric region within the undercut portions and adjacent the lower sidewall surfaces, and where the step of forming the first conductive region comprises forming a shield electrode, and where the step of forming the second conductive region comprising forming a gate electrode, and where the method further comprises the steps of:

forming a body region adjacent the trench; and

forming a source region within the body region and adjacent trench.

17. A semiconductor device structure comprising:

a region of semiconductor material having a trench extending from a major surface, where the trench has sidewall surfaces and a lower surface;

an insulated shield electrode formed within the trench, where the insulated shield electrode includes an insulating layer, a shield electrode adjacent the insulating layer, and a first dielectric region adjacent an upper surface of the shield electrode, where the insulating layer has a variable thickness along lower portions of the sidewall surfaces with a thicker portion in proximity to the lower surface;

an insulated gate electrode formed within the trench above the insulated shield electrode, where the insulated gate electrode includes a gate dielectric layer adjacent upper surfaces if the trench and a gate electrode adjacent the gate dielectric layer and the first dielectric region;

a body region adjacent the trench; and

a source region adjacent the trench.

18. The structure of claim 17 further comprising a layer of material formed between the shield electrode and the region of semiconductor material, where the layer of material has a gap between adjacent portions of the layer of material in proximity to the lower surface.

19. The structure of claim 18, where the layer of material comprises a silicon nitride

20. The structure of claim 17, where the shield electrode has a stepped shaped.