DISPLAY PIXEL HAVING OXIDE THIN-FILM TRANSISTOR (TFT) WITH REDUCED LOADING

• US 20120327321A1
• Filed: 09/23/2011
• Published: 12/27/2012
• Est. Priority Date: 06/23/2011
• Status: Active Grant

• Current Assignee: Curis, Inc.
• Original Assignee: Apple Inc.
• Inventors: Park, Young Bae, Chang, Shih Chang, Huang, Chun-Yao
• Granted Patent: US 8,988,624 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed embodiments relate to a thin-film transistor (TFT) for use in a display device. The display device may include a liquid crystal display (LCD) panel having multiple pixels arranged in rows and column, with each row corresponding to a gate line and each column corresponding to a source line. Each of the pixels includes a pixel electrode and a TFT. The TFT may include a metal oxide semiconductor channel between a source and drain. For each TFT, holes may be formed in the gate line in a region beneath the source and/or the drain. The holes may be formed such that the source and drain only partially overlap the holes. The presence of the holes reduces the area of the gate line, which may reduce parasitic capacitance and improve loading. This may provide improved panel performance, which may reduce the appearance of certain visual artifacts.

Claims

1. A display device comprising:

a liquid crystal display (LCD) panel comprising a plurality of display pixels arranged in rows and column, wherein each of the display pixels comprises;

a pixel electrode; and

a thin-film transistor (TFT) coupled to a source line and a gate line, wherein the TFT comprises a source, a channel, and a drain, and wherein the gate line comprises a first hole that is at least partially overlapped by the drain and configured to reduce parasitic capacitance by decreasing the area of the gate line.

2. The display device of claim 1, wherein the channel comprises a metal oxide semiconductor material.

3. The display device of claim 1, wherein the reduction in parasitic capacitance decreases loading in the gate line.

4. The display device of claim 1, wherein the gate line comprises a second hole formed at least partially beneath the source of the TFT, wherein the source at least partially overlaps the second hole.

5. A method for manufacturing a thin-film transistor (TFT) for a display device, comprising:

providing a substrate;

forming a gate line over the substrate, wherein the gate line defines a gate for the TFT;

forming at least one hole in the gate line, wherein forming the at least one hole comprises forming a first hole in a region of the gate line generally below where a drain of the TFT will be formed;

forming a metal oxide active layer over the gate line;

forming an etch stopper layer over the metal oxide active layer;

forming a first hole and a second hole in the etch stopper layer;

depositing conductive material over the first and second holes to form a source over first hole and a drain over the second hole;

forming an organic passivation layer over the source and drain;

etching a third hole in the organic passivation layer that exposes at least a portion of the drain;

forming a common voltage electrode over the organic passivation layer and the exposed portion of the drain;

etching a fourth hole in the common voltage electrode layer that exposes at least a portion of the organic passivation layer and the drain;

forming a passivation layer over the common voltage electrode layer and the exposed portions of the organic passivation layer and the drain; and

etching a fifth hole that exposes a portion of the drain;

wherein the first hole is at least partially overlapped by the drain.

6. The method of claim 5, comprising forming a pixel electrode over the passivation layer, wherein the pixel electrode contacts the exposed portion of the drain through the fifth hole.

7. The method of claim 5, wherein forming the at least one hole comprises forming a second hole a region of the gate line generally below the source of the TFT, such that the second hole is at least partially overlapped by the source.

8. The method of claim 7, wherein each of the first and second holes formed in the gate line is configured to reduce parasitic capacitance between the gate line and components of the TFT.

9. The method of claim 5, comprising depositing a gate insulation layer over the gate line and before forming the metal oxide active layer.

10. A display device comprising:

a liquid crystal display (LCD) panel comprising a plurality of display pixels arranged in rows and column, wherein each of the display pixels comprises;

a pixel electrode; and

a thin-film transistor (TFT) coupled to a source line and a gate line, wherein the gate line comprises a protrusion extending outwardly in a perpendicular direction, and wherein the TFT comprises;

an L-shaped metal oxide active layer comprising a first portion that is parallel to the gate line and a second portion that is perpendicular to the gate line but parallel to the protrusion;

a source formed at an end of the first portion of the L-shaped metal oxide active layer; and

a drain formed at the end of the second portion of the L-shaped metal oxide active layer, wherein the protrusion is only partially overlapped by the drain.

11. The display device of claim 10, wherein the gate line comprises a hole formed in a region that is generally beneath the source, wherein the source at least partially overlaps the hole.

12. The display device of claim 10, comprising a pixel contact hole formed above the drain, wherein the pixel contact hole is located between a source line connected to the source of the TFT and an adjacent source line.

13. The display device of claim 12, wherein the distance of the pixel contact hole from each of the source line and the adjacent source line is equal.