Low-loss Optical Coupling Apparatus
First Claim
1. A low-loss optical coupling apparatus, comprising a silicon-on-insulator wafer 100, said silicon-on-insulator wafer 100 having a silicon substrate 101;
- a silicon dioxide layer 103, said silicon dioxide layer 103 being located on the silicon substrate 101;
a waveguide layer, said waveguide layer being located on the silicon dioxide layer 103.a waveguide circuit, said waveguide circuit being located on said waveguide layer which comprises a slab region and a waveguide region;
a taper waveguide 111, said taper waveguide 111 being a waveguide circuit which has one larger-width end and one smaller-width end, said larger-width end being connected to an end of the chip;
a channel waveguide 113, said channel waveguide 113 being a waveguide circuit connected to said smaller-width end of said taper waveguide 111; and
a thick-film silicon dioxide layer 109, said thick-film silicon dioxide layer 109 being located on said taper waveguide 111.
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Abstract
A low-loss optical coupling apparatus includes a silicon-on-insulator wafer, a silicon dioxide layer, a taper waveguide, a channel waveguide and a thick-film silicon dioxide layer. The silicon-on-insulator wafer is formed with a silicon substrate. The silicon dioxide layer is provided on the silicon substrate. The taper waveguide comprises a slab region formed on the silicon dioxide layer and a waveguide region formed on the slab region. An end of a chip is connected to an end of the waveguide region. The channel waveguide is formed on the slab region and connected to another end of the waveguide region. The thick-film silicon dioxide layer extends on the taper waveguide and covers the entire waveguide region.
34 Citations
10 Claims
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1. A low-loss optical coupling apparatus, comprising a silicon-on-insulator wafer 100, said silicon-on-insulator wafer 100 having a silicon substrate 101;
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a silicon dioxide layer 103, said silicon dioxide layer 103 being located on the silicon substrate 101; a waveguide layer, said waveguide layer being located on the silicon dioxide layer 103. a waveguide circuit, said waveguide circuit being located on said waveguide layer which comprises a slab region and a waveguide region; a taper waveguide 111, said taper waveguide 111 being a waveguide circuit which has one larger-width end and one smaller-width end, said larger-width end being connected to an end of the chip; a channel waveguide 113, said channel waveguide 113 being a waveguide circuit connected to said smaller-width end of said taper waveguide 111; and a thick-film silicon dioxide layer 109, said thick-film silicon dioxide layer 109 being located on said taper waveguide 111. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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- Resources
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Current AssigneeNational Central University
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Original AssigneeNational Central University
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InventorsLu, Hung-Chih, Chyi, Jen-Inn
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Application NumberUS13/293,228Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current385/14CPC Class CodesG02B 6/1228 Tapered waveguides, e.g. in...G02B 6/124 Geodesic lenses or integrat...
