CONTROL SYSTEM SOFTWARE EXECUTION DURING FAULT DETECTION

• US 20120331339A1
• Filed: 06/21/2011
• Published: 12/27/2012
• Est. Priority Date: 06/21/2011
• Status: Active Grant

• Current Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Original Assignee: Hamilton Sundstrand Corporation (Rtx Corporation)
• Inventors: Schmidt, Jeffery S., Thangavelu, Kamaraj
• Granted Patent: US 8,909,981 B2
• Time in Patent Office: Days
• US Class Current: 714/15
• CPC Class Codes: G05B 9/02 electric
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/167 Error detection by comparing the memory output

Abstract

An example method for uninterrupted execution of control software in an aircraft control system includes creating a plurality of static data copies. A first parity bit is determined for each of the plurality of static data copies. A second parity bit is determined for a first static data copy. A parity fault is detected in the first static data copy if the first parity bit does not match the second parity bit. The system switches to read a second static data copy in response to detecting a parity fault in the first static data copy.

Claims

1. A method for uninterrupted execution of control software in an aircraft control system comprising:

creating a plurality of static data copies;

determining a first parity bit for each of the plurality of static data copies;

determining a second parity bit for a first static data copy;

detecting a parity fault in the first static data copy if the first parity bit does not match the second parity bit; and

switching to read a second static data copy in response to detecting a parity fault in the first static data copy.

2. The method of claim 1, further including writing each static data copy into a random access memory (RAM) in conjunction with determining the first parity bit and reading the first static data copy in conjunction with determining the second parity bit.

3. The method of claim 2, further including mapping a memory management unit (MMU) table of a processor, the MMU table including a logical page having a logical address mapped to a physical page having a physical address mapped to a corresponding static data copy address on the RAM for each of the plurality of static data copies.

4. The method of claim 3, wherein the processor reads the first static data copy by accessing only a first logical page having a first logical address, wherein the first logical address initially points to a first physical page with a first physical address mapped to a first static data copy address on the RAM.

5. The method of claim 4, including reconfiguring each physical address in the MMU table such that the first logical page has a first logical address pointing to a second physical page with a second physical address mapped to a second static data copy location on the RAM.

6. The method of claim 4, wherein the step of switching to read a second static data copy in response to detecting a parity fault in the first static data copy is repeated until the first logical address of the first logical page again points to the first physical page.

7. The method of claim 2, including comparing the plurality of static data copies stored in the RAM to each other to determine a corrupted static data copy responsive to at least one bit not matching a corresponding bit in the remaining plurality of static data copies.

8. The method of claim 7, further including overwriting the corrupted static data copy with another of the plurality of static data copies.

9. The method of claim 7, further comprising the step of overwriting the corrupted static data copy with a new static data copy from a read only memory.

10. The method of claim 1, further comprising the step of generating the first parity bit using a parity generator to employ odd parity, wherein the first parity bit is configured to be set such that each byte of a static data copy will include an odd number of bits having the value 1.

11. A method of data fault correction in a control system during operation in an aircraft comprising:

reading a plurality of static data copies from a random access memory (RAM);

comparing each of the plurality of static data copies to each other;

determining a corrupted static data copy having a parity fault indicating that at least one bit does not match a corresponding bit in the remaining static data copies amongst the plurality of static data copies;

overwriting the corrupted static data copy with a second data copy to remove the parity fault; and

writing each of the plurality of static data copies into the RAM.

12. The method of claim 11, wherein the step of reading the plurality of static data copies from the RAM is performed in response to detection of the parity fault in the control system.

13. The method of claim 11, wherein the second data copy is one of the plurality of static data copies that is not corrupted.

14. The method of claim 11, wherein the step of reading the plurality of static data copies from the RAM is performed prior to detection of the parity fault.

15. An aircraft control system for continual execution of control software during fault detection comprising:

a random access memory (RAM) configured to store a plurality of static data copies;

a processor configured to access a current static data copy for use during operation;

a parity generator configured to generate a first parity bit for each of the plurality of static data copies when the processor writes data to the RAM, wherein the first parity bit is sent to the RAM for storage with the corresponding static data copy, the parity generator configured to generate a second parity bit for each of the plurality of static data copies when each of the plurality of static data copy is read by the processor; and

a parity checker configured to compare the first parity bit and the second parity bit for each static data copy being read, the parity checker configured to notify the processor when the first bit and second bit are not matching indicating a parity fault, wherein the processor is reconfigured to access a new static data copy from the plurality of static data copies in response to the parity fault.

16. The aircraft control system of claim 15, wherein the processor comprises a memory management unit (MMU) including an MMU table having a mapped logical page and a mapped physical page for each of the plurality of static data copies, wherein the logical page is configured to store a logical address pointing to a physical page storing a physical address for each of the plurality of static data copies, wherein a first logical page pointing to a first physical page is configured to be used by the processor to access the current static data copy, wherein each of the plurality of static data copies is stored at a corresponding physical address in the RAM.

17. The aircraft control system of claim 16, wherein the physical pages in the MMU table are reconfigured such that the first logical page points to a second physical page having a physical address mapped to a different static data copy than the first physical page in response to the parity fault.

18. The aircraft control system of claim 15, wherein the plurality of static data copies are configured to be generated by a read only memory and provided to the RAM via the processor.

19. The aircraft control system of claim 15, further comprising a data bus configured to read and write data between the processor and the RAM and an address bus configured to map the physical address of each static data copy in the RAM to the physical address in the corresponding physical page.

20. The aircraft control system of claim 19, wherein the data bus is a 32-bit data bus and the address bus is a 32-bit address bus.