RESISTANCE CHANGE MEMORY AND METHOD OF MANUFACTURING THE SAME

• US 20130001506A1
• Filed: 01/23/2012
• Published: 01/03/2013
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Asao, Yoshiaki, Obara, Takashi, Nakazawa, Takashi, SATO, Motoyuki
• Granted Patent: US 8,779,410 B2
• Time in Patent Office: Days
• US Class Current: 257/5
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

Claims

1. A method of manufacturing a resistance change memory, the memory comprising resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements, wherein the elements are provided in a lattice pattern having a constant pitch, a thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers, and the vias are provided in the holes respectively,

the method comprising:

forming the elements;

forming an insulating material covering the elements;

forming the holes in a self-alignment when the sidewall insulating layers is formed by etching back the insulating material; and

forming the vias in the holes respectively.

2. The method of claim 1,

wherein the etching back is executed to expose the elements to form upper electrodes at the same time of forming the vias, and each of the upper electrodes is connected to one of the vias and one of the elements.

10. The memory of claim 1,

wherein the vias are selected from a group of tungsten, titanium, titanium nitride, copper, tantalum and tantalum nitride.

3. A resistance change memory comprising:

resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements, wherein the elements are provided in a lattice pattern having a constant pitch, a thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers, and the vias are provided in the holes respectively.

4. The memory of claim 3,

wherein each of the sidewall insulating layers includes a first layer comprising a first material and a second layer comprising a second material different from the first material.

5. The memory of claim 3, further comprising:

a first FET connected between a first element and a first via adjacent to each other in the first direction among the elements and the vias;

a second FET connected between a second element and a second via adjacent to each other in the first direction among the elements and the vias;

a first word line connected to a gate of the first FET, and extending to the second direction;

a second word line connected to a gate of the second FET, and extending to the second direction;

a first upper electrode connected to the first element;

a second upper electrode connected to the first via and the second element;

a third upper electrode connected to the second via;

a first bit line connected to the first and third upper electrodes, and extending the first direction; and

a second bit line connected to the second upper electrode, and extending the first direction,

wherein the first and second elements are adjacent to each other in the constant pitch.

6. The memory of claim 3,

wherein the value for contacting the sidewall insulating layers each other is

(√

{square root over (2)}×

F)−

Sm/2,

where 4 F is the constant pitch, and Sm is a size of each of the elements.

7. The memory of claim 3,

wherein a planer shape of each of the elements is a round shape, and a planer shape of each of the vias is a star shape.

8. The memory of claim 4,

wherein the first layer contacts with one of the elements and prevents an oxidation thereof, and the second layer has a dielectric constant lower than that of the first layer.

9. The memory of claim 4,

wherein the first and second materials are selected from a group of silicon nitride, boron nitride, aluminium nitride, silicon oxide, aluminium oxide, magnesium oxide, hafnium oxide, lanthanum oxide, zirconium oxide and yttrium oxide.