SEMICONDUCTOR DEVICE AND METHOD

• US 20130001507A1
• Filed: 04/03/2012
• Published: 01/03/2013
• Est. Priority Date: 04/05/2011
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: CHENG, Kai, Caymax, Matty
• Granted Patent: US 9,196,477 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Abstract

A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

a) providing a substrate;

b) providing a first epitaxial semiconducting layer on top of the substrate; and

c) forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

2. The method according to claim 1, wherein forming a one- or two dimensional repetitive pattern comprises forming the pattern in the substrate or in the first epitaxial semiconducting layer.

3. The method according to claim 1, wherein the process c) is carried out before the process b) and the pattern is formed in the substrate, or wherein the process c) is carried out after the process b) and the pattern is formed in the first epitaxial semiconducting layer.

4. The method according to claim 1, further comprising, subsequent to the process c), providing a second epitaxial semiconducting layer.

5. The method according to claim 1, wherein the pattern has a width or length in the range of about 0.5 to 5 μ

m.

6. The method according to claim 1, wherein the pattern has a depth in the range of about 0.2 to 2 μ

m.

7. The method according to claim 1, wherein the pattern is selected from one or more of a trench, a pit, a slit, a pillar, a pyramid, a square, a rectangle, a hexagon, a multigon, a circle, and an ellipse.

8. The method according to claim 1, further comprising forming a buffer layer on the substrate before forming the first epitaxial semiconducting layer, wherein the buffer layer comprises one or more of:

an initial layer formed on the substrate; and

a second layer forming a buffer comprising AlGaN, wherein the Al content decreases from bottom to top.

9. The method according to claim 1, wherein two or more first III-V epitaxial semiconducting layers are provided, and/or wherein two or more second III-V epitaxial semiconducting layers are provided.

10. The method according to claim 9, wherein the two or more first III-V epitaxial semiconducting layers are two or more further III-V layers form a stack of alternating III-V layers of two or more types, wherein the stack provides a multiple quantum well.

11. A semiconductor device as manufactured according to the method of claim 1.

12. A high current low carrier density semiconductor device having a high break down voltage, the device comprising:

a substrate;

a first epitaxial semiconducting layer on top of the substrate; and

a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.

13. The device according to claim 12, the device further comprising a second epitaxial semiconducting layer on top of the first epitaxial semiconducting layer.

14. The device according to claim 12, wherein the pattern has a width or length in the range of about 0.5 to 5 μ

m.

15. The device according to claim 12, wherein the pattern has a depth in the range of about 0.2 to 2 μ

m.

16. The device according to claim 12, wherein the pattern is selected from one or more of a trench, a pit, a slit, a pillar, a pyramid, a square, a rectangle, a hexagon, a multigon, a circle, and an ellipse.

17. An electronic circuit comprising a semiconductor device according to claim 12.

18. The electronic circuit according to claim 17, the electronic circuit being a transistor, a FET, a HEMT, a DHFET, a LED, a diode, or a power device.

19. An apparatus comprising a semiconductor device according to claim 12, the apparatus being an electronic circuit, a switch, a high power application, a high voltage application, an image sensor, a biosensor, or an ion sensor.