SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20130001568A1
• Filed: 09/11/2012
• Published: 01/03/2013
• Est. Priority Date: 02/23/1999
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, MURAKAMI, Satoshi, KOYAMA, Jun, TANAKA, Yukio, KITAKADO, Hidehito, OHNUMA, Hideto
• Granted Patent: US 8,558,241 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/126 : Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals

Abstract

This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Claims

1. An EL display device comprising a pixel, the pixel comprising:

a thin film transistor comprising;

a first semiconductor layer portion comprising a channel formation region, a first terminal region, and a second terminal region;

a first insulating layer over the first semiconductor layer portion;

a gate electrode layer overlapping the first semiconductor layer portion and over the first insulating layer;

a second insulating layer over the thin film transistor;

a wiring and a current supply line made from a same film formed over the second insulating layer, the wiring being in electrical contact with one of the first terminal region and the second terminal region and the current supply line with the other of the first terminal region and the second terminal region;

a third insulating layer over the wiring and the current supply line;

a first electrode over the third insulating layer, the first electrode being in electrical contact with the wiring;

an EL layer over the first electrode;

a second electrode over the EL layer; and

a capacitor overlapping with the current supply line, the capacitor comprising;

a second semiconductor layer portion;

a portion of the first insulating layer formed over the second semiconductor layer portion; and

a third electrode formed over the first insulating layer from a same film as the gate electrode layer, and overlapping the second semiconductor layer portion,

wherein a portion of the second insulating layer overlaps the third electrode and the second semiconductor layer portion.

5. The EL display device according to claim 1,

wherein the current supply line is in electrical contact with the second semiconductor layer portion.

9. The EL display device according to claim 1,

wherein the current supply line can have a same potential as that of one terminal of the capacitor.

13. The EL display device according to claim 1,

wherein the first semiconductor layer portion and the second semiconductor layer portion are apart from each other.

17. The EL display device according to claim 1,

wherein the other of the first terminal region and the second terminal region is functionally connected to the second semiconductor layer portion.

21. The EL display device according to claim 1,

wherein the current supply line is parallel to a source signal line.

25. The EL display device according to claim 1,

wherein the EL display device is a top emission display device in which light is emitted from the side of the second electrode.

2. An EL display device comprising a pixel, the pixel comprising:

a first thin film transistor comprising;

a first semiconductor layer portion comprising a first channel formation region, a first terminal region, and a second terminal region;

a first insulating layer over the first semiconductor layer portion;

a first gate electrode layer overlapping the first semiconductor layer portion and over the first insulating layer;

a second thin film transistor comprising;

a second semiconductor layer portion comprising a second channel formation region, a third terminal region, and a fourth terminal region;

a portion of the first insulating layer formed over the second semiconductor layer portion;

a second gate electrode layer formed from a same film as the first gate electrode layer and overlapping the second semiconductor layer portion;

a second insulating layer over the first thin film transistor and the second thin film transistor;

a first wiring, a second wiring, and a current supply line made from a same film formed over the second insulating layer, the first wiring being in electrical contact with one of the first terminal region and the second terminal region and the second wiring being in electrical contact with one of the third terminal region and the fourth terminal region;

a third insulating layer over the first wiring, the second wiring, and the current supply line;

a first electrode over the third insulating layer, the first electrode being in electrical contact with the first wiring;

an EL layer over the first electrode;

a second electrode over the EL layer; and

a capacitor overlapping with the current supply line, the capacitor comprising;

a third semiconductor layer portion;

a portion of the first insulating layer formed over the third semiconductor layer portion; and

a third electrode formed from a same film as the first gate electrode layer and overlapping the third semiconductor layer portion,

wherein the current supply line is in electrical contact with the other of the first terminal region and the second terminal region.

6. The EL display device according to claim 2,

wherein the current supply line is in electrical contact with the third semiconductor layer portion.

10. The EL display device according to claim 2,

wherein the current supply line can have a same potential as that of one terminal of the capacitor.

14. The EL display device according to claim 2,

wherein the first semiconductor layer portion, the second semiconductor layer portion, and the third semiconductor layer portion are apart from each other.

18. The EL display device according to claim 2,

wherein the other of the first terminal region and the second terminal region is functionally connected to the second semiconductor layer portion.

22. The EL display device according to claim 2,

wherein the current supply line is parallel to a source signal line.

26. The EL display device according to claim 2,

wherein the EL display device is a top emission display device in which light is emitted from the side of the second electrode.

3. An EL display device comprising a pixel, the pixel comprising:

a first thin film transistor comprising;

a first semiconductor layer portion comprising a first channel formation region, a first terminal region, and a second terminal region;

a first insulating layer over the first semiconductor layer portion;

a first gate electrode layer overlapping the first semiconductor layer portion and over the first insulating layer;

a second thin film transistor comprising;

a second semiconductor layer portion comprising a second channel formation region, a third terminal region, and a fourth terminal region;

a portion of the first insulating layer formed over the second semiconductor layer portion;

a second gate electrode layer formed from a same film as the first gate electrode layer and overlapping the second semiconductor layer portion;

a second insulating layer over the first thin film transistor and the second thin film transistor;

a first wiring, a second wiring, and a current supply line made from a same film formed over the second insulating layer, the first wiring being in electrical contact with one of the first terminal region and the second terminal region, and the second wiring being in electrical contact with one of the third terminal region and the fourth terminal region;

a third insulating layer over the first wiring, the second wiring, and the current supply line;

a first electrode over the third insulating layer, the first electrode being in electrical contact with the first wiring;

an EL layer over the first electrode;

a second electrode over the EL layer; and

a capacitor overlapping with the current supply line, the capacitor comprising;

a third semiconductor layer portion;

a portion of the first insulating layer formed over the third semiconductor layer portion; and

a third electrode formed from a same film as the first gate electrode layer and overlapping the third semiconductor layer portion,

wherein the current supply line is functionally connected to the other of the first terminal region and the second terminal region.

7. The EL display device according to claim 3,

wherein the current supply line is in electrical contact with the third semiconductor layer portion.

11. The EL display device according to claim 3,

wherein the current supply line can have a same potential as that of one terminal of the capacitor.

15. The EL display device according to claim 3,

wherein the first semiconductor layer portion, the second semiconductor layer portion, and the third semiconductor layer portion are apart from each other.

19. The EL display device according to claim 3,

wherein the other of the first terminal region and the second terminal region is functionally connected to the second semiconductor layer portion.

23. The EL display device according to claim 3,

wherein the current supply line is parallel to a source signal line.

27. The EL display device according to claim 3,

wherein the EL display device is a top emission display device in which light is emitted from the side of the second electrode.

4. An EL display device comprising a pixel, the pixel comprising:

a first thin film transistor comprising;

a first semiconductor layer portion comprising a first channel formation region, a first terminal region, and a second terminal region;

a first insulating layer over the first semiconductor layer portion;

a first gate electrode layer overlapping the first semiconductor layer portion and over the first insulating layer;

a second thin film transistor comprising;

a second semiconductor layer portion comprising a second channel formation region, a third terminal region, and a fourth terminal region;

a portion of the first insulating layer formed over the second semiconductor layer portion;

a second gate electrode layer formed from a same film as the first gate electrode layer and overlapping the second semiconductor layer portion;

a second insulating layer over the first thin film transistor and the second thin film transistor;

a first wiring, a second wiring, a third wiring, and a current supply line made from a same film formed over the second insulating layer, the first wiring being in electrical contact with one of the first terminal region and the second terminal region, the second wiring being in electrical contact with one of the third terminal region and the fourth terminal region, and the third wiring being in electrical contact with the other of the third terminal region and the fourth terminal region;

a third insulating layer over the first wiring, the second wiring, and the current supply line;

a first electrode over the third insulating layer, the first electrode being in electrical contact with the first wiring;

an EL layer over the first electrode;

a second electrode over the EL layer; and

a capacitor overlapping with the current supply line, the capacitor comprising;

a third semiconductor layer portion;

a portion of the first insulating layer formed over the third semiconductor layer portion; and

a third electrode formed from a same film as the first gate electrode layer and overlapping the third semiconductor layer portion,

wherein the current supply line is functionally connected to the other of the first terminal region and the second terminal region, and

wherein the first gate electrode is electrically connected to the other of the third terminal region and the fourth terminal region via the third wiring.

8. The EL display device according to claim 4,

wherein the current supply line is in electrical contact with the third semiconductor layer portion.

12. The EL display device according to claim 4,

wherein the current supply line can have a same potential as that of one terminal of the capacitor.

16. The EL display device according to claim 4,

wherein the first semiconductor layer portion, the second semiconductor layer portion, and the third semiconductor layer portion are apart from each other.

20. The EL display device according to claim 4,

wherein the other of the first terminal region and the second terminal region is functionally connected to the second semiconductor layer portion.

24. The EL display device according to claim 4,

wherein the current supply line is parallel to a source signal line.

28. The EL display device according to claim 4,

wherein the EL display device is a top emission display device in which light is emitted from the side of the second electrode.