CHIP PACKAGE AND METHOD FOR FORMING THE SAME

• US 20130001621A1
• Filed: 06/28/2012
• Published: 01/03/2013
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: SHIU, Chuan-Jin, LIN, Po-Shen, CHANG, Yi-Ming
• Granted Patent: US 8,890,191 B2
• Time in Patent Office: Days
• US Class Current: 257/98
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

Claims

1. A chip package, comprising:

a substrate having a first surface and a second surface;

an optoelectronic device formed in the substrate;

a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device;

an insulating layer disposed between the substrate and the conducting layer;

a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and

a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

2. The chip package as claimed in claim 1, further comprising a through-hole extending from the second surface towards the first surface, wherein the insulating layer extends along a sidewall of the through-hole and extends onto the second surface of the substrate, and the conducting layer extends on the insulating layer in the through-hole.

3. The chip package as claimed in claim 2, wherein the light shielding layer extends into the through-hole.

4. The chip package as claimed in claim 3, wherein the light shielding layer is substantially and conformally disposed on the conducting layer on the sidewall of the through-hole.

5. The chip package as claimed in claim 3, wherein the light shielding layer fills the through-hole.

6. The chip package as claimed in claim 3, wherein the light shielding layer completely fills the through-hole.

7. The chip package as claimed in claim 2, wherein the light shielding layer covers the through-hole.

8. The chip package as claimed in claim 7, wherein the light shielding layer does not fill the through-hole.

9. The chip package as claimed in claim 1, wherein the light shielding layer directly contacts with the conducting bump.

10. The chip package as claimed in claim 1, wherein the conducting bump completely fills the opening of the light shielding layer.

11. The chip package as claimed in claim 1, further comprising a transparent substrate disposed on the first surface of the substrate.

12. The chip package as claimed in claim 11, further comprising a spacer layer disposed between the substrate and the transparent substrate, wherein all together the spacer layer, the substrate, and the transparent substrate surround a cavity on the optoelectronic device.

13. A method for forming a chip package, comprising:

providing a substrate having a first surface and a second surface, wherein at least an optoelectronic device is formed in the substrate;

forming an insulating layer on the substrate;

forming a conducting layer on the insulating layer on the substrate, wherein the conducting layer is electrically connected to the at least an optoelectronic device;

forming a light shielding layer on the second surface of the substrate, wherein the light shielding layer directly contacts with the conducting layer and has at least an opening exposing the conducting layer, and the light shielding layer has a light shielding rate of more than about 80%; and

forming a conducting bump in the at least an opening of the light shielding layer to electrically connect to the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

14. The method for forming a chip package as claimed in claim 13, further comprising removing a portion of the substrate from the second surface of the substrate to form a through-hole extending towards the first surface of the substrate before the insulating layer is formed, wherein the insulating layer extends on a sidewall of the through-hole, and the conducting layer extends on the insulating layer in the through-hole.

15. The method for forming a chip package as claimed in claim 14, wherein the light shielding layer extends on the conducting layer in the through-hole.

16. The method for forming a chip package as claimed in claim 13, further comprising performing a dicing process along a plurality of predetermined scribe lines on the substrate to form a plurality of chip packages separated from each other.

17. The method for forming a chip package as claimed in claim 13, wherein the formation of the conducting bump comprises:

filling a solder material into the at least an opening of the light shielding layer; and

performing a reflow process to the solder material to form the conducting bump.

18. The method for forming a chip package as claimed in claim 13, further comprising disposing a transparent substrate on the first surface of the substrate.

19. The method for forming a chip package as claimed in claim 18, further comprising disposing a spacer layer between the substrate and the transparent substrate, wherein all together the spacer layer, the substrate, and the transparent substrate surround a cavity on the optoelectronic device.

20. The method for forming a chip package as claimed in claim 13, wherein the formation of the light shielding layer comprises:

applying a polymer solution on the second surface of the substrate to form a light shielding material layer; and

performing an exposure process and a development process to the light shielding material layer to form the light shielding layer.