MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME

• US 20130001652A1
• Filed: 03/23/2012
• Published: 01/03/2013
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshikawa, Masatoshi, Harakawa, Hideaki, Kishi, Tatsuya, Hosotani, Keiji, Seto, Satoshi, Ozeki, Jyunichi
• Granted Patent: US 8,716,818 B2
• Time in Patent Office: Days
• US Class Current: 257/252
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

Claims

1. A magnetoresistive element comprising:

a storage layer having a variable and perpendicular magnetization;

a tunnel barrier layer on the storage layer;

a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer;

a hard mask layer on the reference layer; and

a side wall spacer layer on side walls of the reference layer and the hard mask layer,

wherein an in-plane size of the reference layer is smaller than an in-plane size of the storage layer, a difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less, and the side wall spacer layer comprises a material selected from a group of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

2. The element of claim 1,

wherein the side wall spacer layer includes a stacked structure comprising layers, and an uppermost layer of the stacked structure comprises the material.

3. The element of claim 1,

wherein an in-plane size of the side wall spacer is 1 nm or less.

4. The element of claim 1,

wherein the side wall spacer includes a re-deposition layer which is formed by patterning of the reference layer.

5. The element of claim 1,

wherein the hard mask layer comprises a material selected from a group of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN.

6. The element of claim 1,

wherein the side wall spacer layer and the hard mask layer comprises the same material.

7. The element of claim 1,

wherein an in-plane shape of the reference layer is a circular shape.

8. The element of claim 1,

wherein an in-plane shape of the reference layer is an elliptical shape.

9. The element of claim 1,

wherein the tunnel barrier layer comprises MgO.

10. The element of claim 1, further comprising:

a sift adjustment layer between the reference layer and the hard mask layer, the sift adjustment layer which adjusts a shift of a magnetic hysteresis curve of the storage layer.

11. The element of claim 10,

wherein the sift adjustment layer comprises a material selected from a group of Pt, Pd and Ir.

12. The element of claim 1, further comprising:

a protection layer covering the reference layer and the storage layer, the protection layer which protects the reference layer and the storage layer from H2O and O2.

13. The element of claim 12,

wherein the protection layer comprises a material selected from a group of SiN, AlN and BN.

14. The element of claim 1, further comprising:

a boundary layer between the tunnel barrier layer and the reference layer.

15. The element of claim 1,

wherein a magnetization of the storage layer is reversed by a spin-momentum-transfer.

20. A magnetic random access memory comprising:

the element of claim 1;

FET having first and second switch terminals and a control terminal, the first switch terminal connected to one of the storage layer and the reference layer of the element;

a word line connected to the control terminal of the FET;

a first bit line connected to the other one of the storage layer and the reference layer of the element;

a second bit line connected to the second switch terminal of the FET;

a first control circuit controlling a potential of the word line; and

a second control circuit controlling potentials of the first and second bit lines.

16. A method of manufacturing a magnetoresistive element,

the element comprising:

a storage layer having a variable and perpendicular magnetization;

a tunnel barrier layer on the storage layer;

a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer;

a hard mask layer on the reference layer; and

a side wall spacer layer on side walls of the reference layer and the hard mask layer,

wherein an in-plane size of the reference layer is smaller than an in-plane size of the storage layer, a difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less, and the side wall spacer layer comprises a material selected from a group of a diamond, DLC, BN, SiC, B₄C, Al₂O₃ and AlN,

the method comprising;

patterning the reference layer by a first etching using the hard mask layer as an etching mask;

forming the side wall spacer layer on the side wall of the hard mask layer and the reference layer; and

patterning the storage layer by a second etching using the hard mask layer and the side wall spacer layer as an etching mask,

wherein the patterning the reference layer and the forming the side wall spacer layer are continuously executed in vacuum.

17. The method of claim 16, further comprising:

generating a gas which comprises one selected from a group of He, H2, Ne, Ar, Xe, Kr, N2, CO, CO2 and CH₃OH in the first and second etchings.

18. The method of claim 16,

wherein each of the first and second etchings is an ion beam etching.

19. The method of claim 16,

wherein the forming the side wall spacer layer is executed in a temperature of 300°

C. or less.