FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION

• US 20130001683A1
• Filed: 08/26/2012
• Published: 01/03/2013
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Pan, Ji, Ng, Daniel, Bhalla, Anup, Wang, Xiaobin
• Granted Patent: US 8,692,322 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

Claims

1. A semiconductor power device comprising a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein said trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer wherein:

at least one of the transistor cells having the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

2. The semiconductor power device of claim 1 wherein:

said semiconductor substrate further includes an active region and a termination region and said transistor cells in said active region having a source region disposed next to the trenched gate; and

at least one of said transistor cells constituting a source contacting cell comprising a source connecting trench opened in said source region filled with a conductive material for electrically connecting said source-connecting shielding bottom electrodes to a source metal disposed directly on top of said source connecting trench.

3. The semiconductor power device of claim 1 wherein:

said semiconductor substrate further includes an active region and a termination region and said gate trench further having gate-pad contact trenches disposed at the termination region and said gate trench further having a plurality gate runner trenches extended from the gate trenches in the active region to the gate-pad contact trenches in the termination region;

at least one of said gate-pad contact trenches functioning as a shielding-bottom-to-gate-pad contact trench filled with a conductive material for electrically connecting at least one of said gate connecting shielding bottom electrodes to a gate metal disposed directly on top of said shield-bottom-to-gate-pad contacting trench.

4. The semiconductor power device of claim 2 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a plurality of source openings on top of said source region and said source connecting trench, wherein a conductive material is filled in to said plurality of source openings for electrically connecting the source region and the source-connecting shielding bottom electrode to said source metal.

5. The semiconductor power device of claim 2 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a plurality of gate openings on top of said gate-pad contact trenches with said shielding-bottom-to-gate-pad contact trench in said termination region for electrically connecting trenched gates and the gate-connecting shielding bottom electrode to said gate-pad.

6. The semiconductor power device of claim 3 wherein:

at least one of said gate-pad contact trenches filled with a conductive material for electrically connecting only to the top gate electrode and is electrically shielding from the shielding bottom electrode disposed in a bottom portion of the trenched gates.

7. The semiconductor power device of claim 3 further comprising

a dummy trench disposed in a periphery of the termination area opened through an insulation protective layer disposed on top of said semiconductor power device wherein said dummy trench is filled with a metal plug on top of the conductive material filling in a bottom portion of the dummy trench wherein the metal plug in the dummy trench further contacts a drain metal covering the insulation protective layer at the periphery of the termination area to function as a channel stop of the semiconductor power device.

8. The semiconductor power device of claim 3 wherein:

said gate runner trenches further comprising the shielding bottom electrode disposed in a bottom portion of the gate runner trenches electrically insulated from the top gate electrode by the inter-electrode insulation layer.

9. The semiconductor power device of claim 1 wherein:

a ratio of a number, of the transistor cells having the gate-connecting shielding bottom electrode electrically connected to a gate metal to a number of the transistor cells having the source-connecting shielding bottom electrode electrically connected to a source electrode is between 1% to 50%.

10. The semiconductor power device of claim 9 wherein:

a ratio of a number of the transistor cells having the gate-connecting shielding bottom electrode electrically connected to a gate metal to a number of the transistor cells having the source-connecting shielding bottom electrode electrically connected to a source electrode is 25%.

11. The semiconductor power device of claim 10 wherein:

a number of the transistor cells having the source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device is about four times of a number of the transistor cells having the gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

12. The semiconductor power device of claim 9 wherein:

a ratio of a number of the transistor cells having the gate-connecting shielding bottom electrode electrically connected to a gate metal to a number of the transistor cells having the source-connecting shielding bottom electrode electrically connected to a source electrode is 50%.

13. The semiconductor power device of claim 12 wherein:

a number of the transistor cells having the source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device is about twice of a number of the transistor cells having the gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

14. A method for manufacturing a semiconductor power device comprising a source metal and a gate metal electrically connected to a source and gate of the semiconductor power device respectively, wherein the method comprising:

opening a plurality of trenches in a substrate and filling said trench with a conductive gate material; and

applying a mask for carrying out a time etch for etching back said gate material from selected trenches, each adjacent to active transistor cells, thus leaving a bottom portion in said selected trenches and leaving the trenches covered by the mask still filled with the gate conductive material;

covering the bottom portion in said selected trenches with a shielding insulation to form a bottom shielding electrode;

designating some of the trenches still filled with the conductive gate material as source contact trenches for contacting the source metal and reminder of the trenches filled with the conductive gate material as gate contact trenches for contacting to the gate metal; and

electrically contacting a first predetermined set of the bottom shielding electrodes to at least one of the source contact trench and a second predetermined set of the bottom shielding electrodes to at least one of the gate contact trenches.

15. The method of claim 14 further comprising:

the step of forming the gate contact trenches further comprising a step of forming the gate contact trenches in a termination area away from the active cells for contacting the gate metal covering over the termination area.

16. The method of claim 14 further comprising:

the step of forming the source contact trenches further comprising a step of forming the source contact trenches in an active cell area adjacent to the active cells for contacting the source metal covering over the active cell area.

17. The method of claim 14 further comprising:

the step of said electrically connecting respectively the first predetermined set and the second predetermined set of the bottom shielding electrodes to the source contact trenches and the gate metal further comprising a step of configuring the second predetermined set about 1% to 50% of the first predetermined set of the bottom shielding electrodes.

18. The method of claim 14 further comprising:

forming an insulation layer for covering a top surface of said semiconductor power device and opening a plurality of source contact openings on top of said remainder portion of said trench to form source contact to direct contact said gate material in said remainder portion of said trench for electrically connecting to said bottom shielding electrode.

19. The method of claim 14 further comprising:

forming an insulation layer for covering a top surface of said semiconductor power device and opening a at least a gate contact opening for providing a gate pad to electrically connecting to said gate material in said trenched gate in said selected portion of said trench.

20. The method of claim 14 wherein:

the step of opening the plurality of trenches further comprising a step of opening a plurality gate runner trenches extended from gate trenches in an active area near the active transistor cells to the gate-contacting trenches disposed in an termination area; and

the step of electrically connecting the second predetermined set of bottom shielding electrodes to the gate-contacting trenches further comprising a step of filling the gate runner trenches with the conductive gate material for electrically connecting the second predetermined set of bottom shielding electrodes to the gate-contacting trenches through the gate runner trenches.