SEMICONDUCTOR DEVICE

• US 20130001703A1
• Filed: 04/15/2011
• Published: 01/03/2013
• Est. Priority Date: 04/15/2010
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited), Yoshitaka Sugawara
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited), Yoshitaka Sugawara
• Inventors: Sugawara, Yoshitaka
• Granted Patent: US 8,786,024 B2
• Time in Patent Office: Days
• US Class Current: 257/378
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.

Claims

1. A semiconductor device having at least one or more bipolar transistors and at least one or more unipolar transistors disposed on a semiconductor substrate of a first conductivity type and made of a semiconductor material with a band gap larger than silicon, the semiconductor device comprising:

a first semiconductor layer of the first conductivity type and constituting the semiconductor substrate on a first principal surface side of the semiconductor substrate;

a second semiconductor layer of the first conductivity type and constituting the semiconductor substrate on a second principal surface side of the semiconductor substrate, the second semiconductor layer having an impurity concentration higher than the first semiconductor layer;

a third semiconductor layer of the first conductivity type disposed between the first semiconductor layer and the second semiconductor layer to be in contact with at least the first semiconductor layer;

a concave portion disposed on the second principal surface side of the semiconductor substrate and penetrating the second semiconductor layer to the third semiconductor layer;

a fourth semiconductor layer of a second conductivity type and disposed on a bottom surface of the concave portion to be in contact with the third semiconductor layer;

an output electrode of the bipolar transistor, contacting the fourth semiconductor layer;

an input electrode and a control electrode of the bipolar transistor disposed on the first principal surface side of the semiconductor substrate at a position corresponding to the concave portion;

a convex portion formed on the second principal surface side of the semiconductor substrate, correspondingly to the concave portion;

an output electrode of the unipolar transistor disposed on a surface of the convex portion to be electrically connected to the output electrode of the bipolar transistor;

an input electrode of the unipolar transistor disposed on the first principal surface side of the semiconductor device at a position corresponding to the convex portion to be electrically connected to the input electrode of the bipolar transistor; and

a control electrode of the unipolar transistor disposed on the first principal surface side of the semiconductor device at a position corresponding to the convex portion to be electrically connected to the control electrode of the bipolar transistor.

2. The semiconductor device of claim 1, wherein the unipolar transistor and the bipolar transistor are electrically connected in parallel.

3. The semiconductor device of claim 1, wherein

a plurality of the concave portions is disposed,

the bipolar transistor is disposed at each of the positions corresponding to the concave portions of the semiconductor substrate, and

the input electrodes, the output electrodes, and the control electrodes of the bipolar transistors are respectively electrically connected.

4. The semiconductor device of claim 1, wherein

a plurality of the convex portions is disposed,

the unipolar transistor is disposed at each of the positions corresponding to the convex portions of the semiconductor substrate, and

the input electrodes, the output electrodes, and the control electrodes of the unipolar transistors are respectively electrically connected.

5. The semiconductor device of claim 1, wherein

the bipolar transistor is formed by a plurality of bipolar transistor cells, and

input electrodes, output electrodes, and control electrodes of the bipolar transistor cells are respectively electrically connected.

6. The semiconductor device of claim 1, wherein

the unipolar transistor is formed by a plurality of unipolar transistor cells, and

input electrodes, output electrodes, and control electrodes of the unipolar transistor cells are respectively electrically connected.

7. The semiconductor device of claim 1, further comprising

a fifth semiconductor layer of the second conductivity type of the bipolar transistor selectively disposed on a surface layer of the first semiconductor layer at a position corresponding to the concave portion;

and

a sixth semiconductor layer of the first conductivity type of the bipolar transistor selectively disposed on a surface layer of the fifth semiconductor layer, wherein

the input electrode of the bipolar transistor is in contact with the sixth semiconductor layer.

8. The semiconductor device of claim 1, further comprising

a seventh semiconductor layer of the second conductivity type of the unipolar transistor selectively disposed on a surface layer of the first semiconductor layer at a position corresponding to the convex portion;

and

an eighth semiconductor layer of the first conductivity type of the unipolar transistor selectively disposed on a surface layer of the seventh semiconductor layer, wherein

the input electrode of the unipolar transistor is in contact with the eighth semiconductor layer.

9. The semiconductor device of claim 1, wherein

the bipolar transistor has an insulation gate structure with a gate insulating film disposed to be in contact with the semiconductor substrate between the semiconductor substrate and the control electrode of the bipolar transistor, and

the unipolar transistor has an insulation gate structure with a gate insulating film disposed to be in contact with the semiconductor substrate, between the semiconductor substrate and the control electrode of the unipolar transistor.

10. The semiconductor device of claim 1, further comprising:

a sixth semiconductor layer of the first conductivity type of the bipolar transistor selectively disposed on a surface layer of the first semiconductor layer at a position corresponding to the concave portion;

a ninth semiconductor layer of the second conductivity type of the bipolar transistor selectively disposed away from the sixth semiconductor on the surface layer of the first semiconductor layer at the position corresponding to the concave portion;

an eighth semiconductor layer of the first conductivity type of the unipolar transistor selectively disposed on the surface layer of the first semiconductor layer at a position corresponding to the convex portion; and

a tenth semiconductor layer of the second conductivity type of the unipolar transistor selectively disposed away from the eighth semiconductor layer on the surface layer of the first semiconductor layer, at the position corresponding to the convex portion, wherein

the bipolar transistor has a gate structure with the control electrode of the bipolar transistor disposed to be in contact with the ninth semiconductor layer, and

the unipolar transistor has a gate structure with the control electrode of the unipolar transistor disposed to be in contact with the tenth semiconductor layer.

11. The semiconductor device of claim 1, wherein

the fourth semiconductor layer is an epitaxial layer grown on a surface of the third semiconductor layer exposed on the bottom surface of the concave portion.

12. The semiconductor device of claim 1, wherein

the fourth semiconductor layer is a semiconductor layer formed by implanting a second conductivity type impurity into the third semiconductor layer exposed on the bottom surface of the concave portion.

13. The semiconductor device of claim 1, further comprising an electric field relaxation layer surrounding the bipolar transistor and the unipolar transistor.

14. The semiconductor device of claim 13, wherein the electric field relaxation layer is disposed on the semiconductor substrate at a position corresponding to a convex portion disposed on an outer peripheral portion.

15. The semiconductor device of claim 1, wherein the third semiconductor layer is in contact with the second semiconductor layer.