FILM STACK INCLUDING METAL HARDMASK LAYER FOR SIDEWALL IMAGE TRANSFER FIN FIELD EFFECT TRANSISTOR FORMATION
First Claim
Patent Images
1. A method for formation of a fin field effect transistor (FinFET) device, the method comprising:
- forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer;
forming a large feature (FX) mask on the metal hardmask layer;
etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer;
etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
7 Assignments
0 Petitions
Accused Products
Abstract
A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.
18 Citations
20 Claims
-
1. A method for formation of a fin field effect transistor (FinFET) device, the method comprising:
-
forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A film stack for formation of a fin field effect transistor (FinFET) device, comprising:
-
a buried oxide (BOX) layer; a silicon on insulator (SOI) layer located on the BOX layer; a thermal silicon oxide layer located on top of the SOI layer; an amorphous carbon layer located on top of the thermal silicon oxide layer; and a metal hardmask layer located on top of the amorphous carbon layer. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification