DELAY CONTROL DEVICE

• US 20130002329A1
• Filed: 09/11/2012
• Published: 01/03/2013
• Est. Priority Date: 03/26/2010
• Status: Abandoned Application

• Current Assignee: Furukawa Automotive Systems Incorporated (Furukawa Electric Company Limited), Furukawa Electric Company Limited
• Original Assignee: Furukawa Automotive Systems Incorporated (Furukawa Electric Company Limited), Furukawa Electric Company Limited
• Inventors: Kamimura, Kazutaka, Aoyagi, Yasushi, MUROFUSHI, Noritaka
• Application Number:
  US13/609,295
• Publication Number:
  US 20130002329A1
• Time in Patent Office: Days
• US Class Current: 327/231
• CPC Class Codes: G01S 13/0209 Systems with very large relative bandwidth, i.e. larger than 10 %, e.g. baseband, pulse, carrier-free, ultrawideband
• CPC Class Codes: G01S 13/18 wherein range gates are used
• CPC Class Codes: G01S 7/032 Constructional details for solid-state radar subsystems
• CPC Class Codes: G01S 7/2921 based on data belonging to one radar period
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A delay control device that controls a relative delay time between two signals and is easy to be miniaturized is provided. Signal routes 111 to 114 and signal routes 121 to 124 in a first signal route part 110 and a second signal route part 120 have different delay times. By selecting any one of the four signal routes 111 to 114 in the first signal route part 110 and any one of the four signal routes 121 to 124 in the second signal route part 120, it is possible to finely change a relative delay time between two input pulse signals.

Claims

1. A delay control device that receiving inputs of a first input pulse signal and a second input pulse signal and outputting a first output pulse signal and a second output pulse signal having a relative delay time near a predetermined target value, the device comprising:

a first input end receiving the input of the first input pulse signal;

a second input end receiving the input of the second input pulse signal;

a first output end outputting the first output pulse signal;

a second output end outputting the second output pulse signal;

a first signal route part having two or more signal routes with different delay times;

a second signal route part having two or more signal routes with different delay times;

a first switch having one connection end formed of two or more terminals connecting one end of each of two or more signal routes of the first signal route part and another connection end formed of one terminal;

a second switch having one connection end formed of two or more terminals connecting one end of each of two or more signal routes of the second signal route part and another connection end formed of one terminal; and

a control part outputting a control signal to the first switch and the second switch so that a relative delay time between the first output pulse signal and the second output pulse signal is near the target value, the control signal for selecting any one of the terminals of the one connection end of the first switch and connecting the selected terminal to the terminal of the other connection end of the first switch and for selecting any one of the terminals of the one connection end of the second switch and connecting the selected terminal to the terminal of the other connection end of the second switch, wherein

the first signal route part and the first switch are connected between the first input end and the first output end, and

the second signal route part and the second switch are connected between the second input end and the second output end.

2. The delay control device according to claim 1, wherein

the signal routes of the first signal route part and/or the second signal route part are configured so that the delay times are different among the signal routes by providing 0 or one or more NOT gates cascade-connected to each other on the signal routes.

3. The delay control device according to claim 2, wherein

the control part

connects the first switch to one of signal routes passing through 0 or an even number of NOT gates or one of signal routes passing through an odd number of NOT gates in the first signal route part according to whether the first input pulse signal is a non-inversion signal or an inversion signal, and connects the second switch to one of signal routes passing through 0 or an even number of NOT gates or one of signal routes passing through an odd number of NOT gates in the second signal route part according to whether the second input pulse signal is a non-inversion signal or an inversion signal.

4. The delay control device according to any one of claims 1 to 3, wherein

two or more signal routes of the first signal route part each have an output side connected to the one connection end of the first switch and an input side merged to be connected to the first input end,

the other connection end of the first switch is connected to the first output end,

two or more signal routes of the second signal route part each have an output side connected to the one connection end of the second switch and an input side merged to be connected to the second input end, and

the other connection end of the second switch is connected to the second output end.

5. The delay control device according to any one of claims 1 to 3, wherein

the other connection end of the first switch is connected to the first input end,

two or more signal routes of the first signal route part each have an input side connected to the one connection end of the first switch and an output side merged to be connected to the first output end,

the other connection end of the second switch is connected to the second input end, and

two or more signal routes of the second signal route part each have an input side connected to the one connection end of the second switch and an output side merged to be connected to the second output end.

6. The delay control device according to any one of claims 1 to 3, wherein

two said first switches and two said second switches are provided and connected to an input side and an output side of the first signal route part and an input side and an output side of the second signal route part,

the other connection end of the first switch connected to the input side of the first signal route part is connected to the first input end and the other connection end of the first switch connected to the output side of the first signal route part is connected to the first output end, and

the other connection end of the second switch connected to the input side of the second signal route part is connected to the second input end and the other connection end of the second switch connected to the output side of the second signal route part is connected to the second output end.

7. The delay control device according to any one of claims 1 to 6, wherein

the first input pulse signal is a non-inversion signal, and

the first signal route part is configured so that the two or more signal routes each pass through a different number, which is 0 or an even number, of NOT gates.

8. The delay control device according to any one of claims 1 to 6, wherein

the first input pulse signal is an inversion signal, and

the first signal route part is configured so that the two or more signal routes each pass through a different odd number of NOT gates.

9. The delay control device according to any one of claims 1 to 6, wherein

the first input pulse signal is an non-inversion signal or an inversion signal,

the first signal route part has a first sub signal route part formed of two or more signal routes each passing through a different number, which is 0 or an even number, of NOT gates and a second sub signal route part formed of two or more signal routes each passing through a different odd number of NOT gates, and

the control part outputs a control signal for selecting one of the signal routes in the first sub signal route part to the first switch when the first input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the second sub signal route part to the first switch when the first input pulse signal is an inversion signal.

10. The delay control device according to any one of claims 1 to 9 wherein

the second input pulse signal is a non-inversion signal, and

the second signal route part is configured so that the two or more signal routes each pass through a different number, which is 0 or an even number, of NOT gates.

11. The delay control device according to any one of claims 1 to 9, wherein

the second input pulse signal is an inversion signal, and

the second signal route part is configured so that the two or more signal routes each pass through a different odd number of NOT gates.

12. The delay control device according to any one of claims 1 to 9, wherein

the second input pulse signal is an non-inversion signal or an inversion signal,

the second signal route part has a third sub signal route part formed of two or more signal routes passing through a different number, which is 0 or an even number, NOT gates and a fourth sub signal route part formed of two or more signal routes each passing through a different odd number of NOT gates, and

the control part outputs a control signal for selecting one of the signal routes in the third sub signal route part to the second switch when the second input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the fourth sub signal route part to the second switch when the second input pulse signal is an inversion signal.

13. The delay control device according to any one of claims 1 to 3, wherein

the first input pulse signal is a non-inversion signal, and

the first signal route part has

a first main signal route having N₁ (N₁ is an even number equal to or larger than 2) NOT gates cascade-connected to each other and

a branch signal route branched from the first main signal route immediately before an M₁-th (M₁=1, 3, . . . , N₁−

1) NOT gate of the N₁ NOT gates or a branch signal route merged to the first main signal route immediately after an L₁-th (L₁=2, 4, . . . , N₁) NOT gate of the N₁ NOT gates.

14. The delay control device according to any one of claims 1 to 3, wherein

the first input pulse signal is an inversion signal, and

the first signal route part has

a second main signal route having N₂ (N₂ is an odd number equal to or larger than 3) NOT gates cascade-connected to each other and

a branch signal route branched from the second main signal route immediately after an M₂-th (M₂=1, 3, . . . , N₂−

2) NOT gate of the N₂ NOT gates or a branch signal route merged to the second main signal route immediately after an L₂-th (L₂=2, 4, . . . , N₂−

1) NOT gate of the N₂ NOT gates.

15. The delay control device according to any one of claims 1 to 3, wherein

the first input pulse signal is a non-inversion signal or an inversion signal,

the first signal route part has

(1) a first sub signal route part having a first main signal route having N₁ (N₁ is an even number equal to or larger than 2) NOT gates cascade-connected to each other, and a branch signal route branched from the first main signal route immediately before an M₁-th (M₁=1, 3, . . . , N₁−

1) NOT gate of the N₁ NOT gates or a branch signal route merged to the first main signal route immediately after an L₁-th (L₁=2, 4, . . . , N₁) NOT gate of the N₁ NOT gates and

(2) a second sub signal route part having a second main signal route having N₂ (N₂ is an odd number equal to or larger than

     3) NOT gates cascade-connected to each other, and a branch signal route branched from the second main signal route immediately after an M₂-th (M₂=1, 3, . . . , N₂−

2) NOT gate of the N₂ NOT gates or a branch signal route merged to the second main signal route immediately after an L₂-th (L₂=2, 4, . . . , N₂−

1) NOT gate of the N₂ NOT gates, and

the control part outputs a control signal for selecting one of the signal routes in the first sub signal route part to the first switch when the first input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the second sub signal route part to the first switch when the first input pulse signal is an inversion signal.

16. The delay control device according to any one of claims 1 to 3 and 13 to 15, wherein

the second input pulse signal is a non-inversion signal, and

the second signal route part has

a third main signal route having N₃ (N₃ is an even number equal to or larger than 2) NOT gates cascade-connected to each other, and

a branch signal route branched from the third main signal route immediately before an M₃-th (M₃=1, 3, . . . , N₃−

1) NOT gate of the N₃ NOT gates or a branch signal route merged to the third main signal route immediately after an L₃-th (L₃=2, 4, . . . , N₃) NOT gate of the N₃ NOT gates.

17. The delay control device according to any one of claims 1 to 3 and 13 to 15, wherein

the second input pulse signal is an inversion signal, and

the second signal route part has

a fourth main signal route having N₄ (N₄ is an odd number equal to or larger than 3) NOT gates cascade-connected to each other, and

a branch signal route branched from the fourth main signal route immediately after an M₄-th (M₄=1, 3, . . . , N₄−

2) NOT gate of the N₄ NOT gates or a branch signal route merged to the fourth main signal route immediately after an L₄-th (L₄=2, 4, . . . , N₄−

1) NOT gate of the N₄ NOT gates.

18. The delay control device according to any one of claims 1 to 3 and 13 to 15, wherein

the second input pulse signal is a non-inversion signal or an inversion signal,

the second signal route part has

(1) a third sub signal route part having a third main signal route having N₃ (N₃ is an even number equal to or larger than 2) NOT gates cascade-connected to each other, and a branch signal route branched from the third main signal route immediately before an M₃-th (M₃=1, 3, . . . , N₃−

1) NOT gate of the N₃ NOT gates or a branch signal route merged to the third main signal route immediately after an L₃-th (L₃=2, 4, . . . , N₃) NOT gate of the N₃ NOT gates and

(2) a fourth sub signal route part having a fourth main signal route having N₄ (N₄ is an odd number equal to or larger than

     3) NOT gates cascade-connected to each other, and a branch signal route branched from the fourth main signal route immediately after an M₄-th (M₄=1, 3, . . . , N₄−

2) NOT gate of the N₄ NOT gates or a branch signal route merged to the fourth main signal route immediately after an L₄-th (L₄=2, 4, . . . , N₄−

1) NOT gate of the N₄ NOT gates, and

the control part outputs a control signal for selecting one of the signal routes in the third sub signal route part to the second switch when the second input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the fourth sub signal route part to the second switch when the second input pulse signal is an inversion signal.

19. The delay control device according to any one of claims 1 to 3, wherein

the first input pulse signal is a non-inversion signal or an inversion signal,

the first signal route part has a first main signal route having a plurality of NOT gates cascade-connected to each other and also has

(1) a first sub signal route part formed of a plurality of signal routes each passing through a different even number of NOT gates from an input side of the first main signal route to the one connection end of the first switch by being branched midway from the first main signal route or passing through the entire first main signal route, and a second sub signal route part formed of a plurality of signal routes each passing through a different odd number of NOT gates from the input side of the first main signal route to the one connection end of the first switch by being branched midway from the first main signal route or passing through the entire first main signal route or

(2) a first sub signal route part formed of a plurality of signal routes each passing through a different even number of NOT gates from the one connection end of the first switch to an output side of the first main signal route by being merged midway to the first main signal route or passing through the entire first main signal route, and a second sub signal route part formed of a plurality of signal routes each passing through a different odd number of NOT gates from the one connection end of the first switch to the output side of the first main signal route by being merged midway to the first main signal route or passing through the entire first main signal route, and

the control part outputs a control signal for selecting one of the signal routes in the first sub signal route part to the first switch when the first input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the second sub signal route part to the first switch when the first input pulse signal is an inversion signal.

20. The delay control device according to any one of claims 1 to 3 and 19, wherein

the second input pulse signal is a non-inversion signal or an inversion signal,

the second signal route part has a second main signal route having a plurality of NOT gates cascade-connected to each other and also has

(1) a third sub signal route part formed of a plurality of signal routes each passing through a different even number of NOT gates from an input side of the second main signal route to the one connection end of the second switch by being branched midway from the second main signal route or passing through the entire second main signal route, and a fourth sub signal route part formed of a plurality of signal routes each passing through a different odd number of NOT gates from the input side of the second main signal route to the one connection end of the second switch by being branched midway from the second main signal route or passing through the entire second main signal route or

(2) a third sub signal route part formed of a plurality of signal routes each passing through a different even number of NOT gates from the one connection end of the second switch to an output side of the second main signal route by being merged midway to the second main signal route or passing through the entire second main signal route, and a fourth sub signal route part formed of a plurality of signal routes each passing through a different odd number of NOT gates from the one connection end of the second switch to the output side of the second main signal route by being merged midway to the second main signal route or passing through the entire second main signal route, and

the control part outputs a control signal for selecting one of the signal routes in the third sub signal route part to the second switch when the second input pulse signal is a non-inversion signal, and outputs a control signal for selecting one of the signal routes in the fourth sub signal route part to the second switch when the second input pulse signal is an inversion signal.

21. The delay control device according to any one of claims 1 to 20, wherein

the first signal route part, the second signal route part, the first switch, and the second switch, and the control part are configured in a PLD (Programmable Logic Device).