SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device, comprising:
- a semiconductor substrate;
a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and
a plurality of bit lines formed above each of a plurality of the memory units aligned in a column directionan alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, andan end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
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Accused Products
Abstract
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
44 Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory device, comprising:
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a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, the bit lines extending in the column direction with a certain pitch in a row direction orthogonal to the column direction; and a bit line contact provided at an end of the memory units and connecting the memory units and the bit lines, the bit line contact being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A semiconductor memory device, comprising:
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a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction a number of the memory cells that are activated simultaneously to be written or read being greater than a number of the memory units aligned in a row direction. - View Dependent Claims (19, 20)
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Specification