DIGIT LINE COMPARISON CIRCUITS
First Claim
1. An apparatus comprising:
- a first plurality of row address register units, wherein a count of the first plurality of row address register units corresponds to a count of rows that are expected to have at least one memory cell unable to retain data, each of the first plurality of row address register units configured to store a row address corresponding to a respective row containing at least one memory cell unable to retain data;
a second plurality of row address register units, wherein a count of the second plurality of row address register units corresponds to a count of the first plurality of row address register units, each of the second plurality of row address register units operable to store a subset of bits of the row address stored in a respective first plurality of row address register units; and
a plurality of comparator units, each of the comparator units configured to receive a refresh row address and respectively coupled to a corresponding row address register unit of the first plurality of row address register units and a corresponding row address register unit of the second plurality of row address register units, each of the plurality of comparator units operable to compare the received refresh row address to the row address bits stored in the corresponding row address unit of the first plurality of row address register units and to the subset of bits stored in the corresponding row address unit of the second plurality of row address register units and generate a high match signal in the event of a match.
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Accused Products
Abstract
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
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Citations
20 Claims
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1. An apparatus comprising:
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a first plurality of row address register units, wherein a count of the first plurality of row address register units corresponds to a count of rows that are expected to have at least one memory cell unable to retain data, each of the first plurality of row address register units configured to store a row address corresponding to a respective row containing at least one memory cell unable to retain data; a second plurality of row address register units, wherein a count of the second plurality of row address register units corresponds to a count of the first plurality of row address register units, each of the second plurality of row address register units operable to store a subset of bits of the row address stored in a respective first plurality of row address register units; and a plurality of comparator units, each of the comparator units configured to receive a refresh row address and respectively coupled to a corresponding row address register unit of the first plurality of row address register units and a corresponding row address register unit of the second plurality of row address register units, each of the plurality of comparator units operable to compare the received refresh row address to the row address bits stored in the corresponding row address unit of the first plurality of row address register units and to the subset of bits stored in the corresponding row address unit of the second plurality of row address register units and generate a high match signal in the event of a match. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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a plurality of complementary digit line pairs, wherein each of the plurality of digital line pairs corresponds to a respective row address; a plurality of logic circuits, wherein each of the plurality of logic circuits is coupled to a respective digital line pair of the plurality of complementary digit line pairs, each of the plurality of logic circuits configured to provide a comparison indication based on leakage of the respective digital line pair of the plurality of complementary digit line pairs, wherein each of the plurality of logic circuits comprises a pair of cross-coupled transistors; and a plurality of row address register units, a row address register unit of the plurality of row address register units configured to store a respective row address corresponding to a digital line pair based on a comparison indication from a corresponding logic circuit of the plurality of logic circuits identifying leakage of the corresponding digital line pair. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method comprising:
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storing a row address at a first row address register unit in response to detection of leakage of a digital line pair corresponding to the row address; storing a portion of the a row address at a second row address register unit in response to detection of leakage of the digital line pair corresponding to the row address; generating a refresh row address based on a refresh counter; setting a first high match signal based on a match between the refresh row address and the row address; setting a second high match signal based on a match between a portion of the refresh row address and the portion of the row address;
wherein the portion of the refresh row address corresponds to the portion of row address; andrefreshing the row address in response to at least one of the first high match signal and the second high match signal being high. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification