DIGIT LINE COMPARISON CIRCUITS

• US 20130003467A1
• Filed: 09/10/2012
• Published: 01/03/2013
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Klein, Dean A.
• Granted Patent: US 8,446,783 B2
• Time in Patent Office: Days
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4062 Parity or ECC in refresh operations
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Claims

1. An apparatus comprising:

a first plurality of row address register units, wherein a count of the first plurality of row address register units corresponds to a count of rows that are expected to have at least one memory cell unable to retain data, each of the first plurality of row address register units configured to store a row address corresponding to a respective row containing at least one memory cell unable to retain data;

a second plurality of row address register units, wherein a count of the second plurality of row address register units corresponds to a count of the first plurality of row address register units, each of the second plurality of row address register units operable to store a subset of bits of the row address stored in a respective first plurality of row address register units; and

a plurality of comparator units, each of the comparator units configured to receive a refresh row address and respectively coupled to a corresponding row address register unit of the first plurality of row address register units and a corresponding row address register unit of the second plurality of row address register units, each of the plurality of comparator units operable to compare the received refresh row address to the row address bits stored in the corresponding row address unit of the first plurality of row address register units and to the subset of bits stored in the corresponding row address unit of the second plurality of row address register units and generate a high match signal in the event of a match.

2. The apparatus of claim 1, wherein at least one of the respective subset of bits stored in each of the second plurality of row address register units is different from at least another subset of bits stored in another of the second plurality of row address register units.

3. The apparatus of claim 1, wherein a first high match signal is set by a first logic gate responsive to a match between the received refresh row address and the row address bits stored in the first plurality of row address register units, and a second high match signal is set by a second logic gate responsive to a match between the received refresh row address and the subset of bits stored in at least one of the second plurality of row address register units.

4. The apparatus of claim 3, wherein each of the first logic gate and the second logic gate comprise an OR gate.

5. The apparatus of claim 3, wherein a count of times the second high match signal is generated per refresh cycle depends on a count of bits stored as the subset of bits in each respective second plurality of row address register units.

6. The apparatus of claim 3, further comprising a refresh row counter configured to generate the refresh row address.

7. The apparatus of claim 6, wherein the refresh row counter is configured to increment responsive to the first high match signal being set, and further configured halt incrementing responsive to the first high match signal being cleared and the second high match signal being set.

8. An apparatus comprising:

a plurality of complementary digit line pairs, wherein each of the plurality of digital line pairs corresponds to a respective row address;

a plurality of logic circuits, wherein each of the plurality of logic circuits is coupled to a respective digital line pair of the plurality of complementary digit line pairs, each of the plurality of logic circuits configured to provide a comparison indication based on leakage of the respective digital line pair of the plurality of complementary digit line pairs, wherein each of the plurality of logic circuits comprises a pair of cross-coupled transistors; and

a plurality of row address register units, a row address register unit of the plurality of row address register units configured to store a respective row address corresponding to a digital line pair based on a comparison indication from a corresponding logic circuit of the plurality of logic circuits identifying leakage of the corresponding digital line pair.

9. The apparatus of claim 8, further comprising a second plurality of row address register units, a row address register unit of the second plurality of row address register units configured to store a portion of the respective row address corresponding to the digital line pair based on the comparison indication from the corresponding logic circuit identifying leakage of the corresponding digital line pair.

10. The apparatus of claim 9, wherein the portion of the respective row address includes every bit of the respective row address except a most significant bit of the respective row address.

11. The apparatus of claim 9, wherein the portion of the respective row address includes every bit of the respective row address except a three most significant bits of the respective row address.

12. The apparatus of claim 9, further comprising a plurality of comparator units, each of the comparator units configured to compare a received refresh row address to the row address stored in a corresponding row address unit of the plurality of row address register units and to the portion of the row address stored in the corresponding row address unit of the second plurality of row address register units and to set a high match signal based on the comparisons.

13. The apparatus of claim 8, wherein each of the plurality of digital line pairs is coupled to one or more respective memory cells, wherein the leakage of the respective digital line pair of the plurality of complementary digit line pairs is based on leakage of one or more of the respective memory cells.

14. A method comprising:

storing a row address at a first row address register unit in response to detection of leakage of a digital line pair corresponding to the row address;

storing a portion of the a row address at a second row address register unit in response to detection of leakage of the digital line pair corresponding to the row address;

generating a refresh row address based on a refresh counter;

setting a first high match signal based on a match between the refresh row address and the row address;

setting a second high match signal based on a match between a portion of the refresh row address and the portion of the row address;

wherein the portion of the refresh row address corresponds to the portion of row address; and

refreshing the row address in response to at least one of the first high match signal and the second high match signal being high.

15. The method of claim 14, further comprising:

comparing the refresh row address to the row address stored in the first row address unit to determine a match, wherein a match indicates that the refresh row address is same address as the row address; and

comparing the portion of the refresh row address to the portion of the row address stored in the second row address unit to determine a match.

16. The method of claim 14, further comprising:

refreshing the refresh row address in response to the first high match signal being set; and

refreshing the row address in response to the first high match signal being cleared and the second high match signal being set.

17. The method of claim 16, further comprising incrementing the refresh counter after refreshing the refresh row address.

18. The method of claim 16, further comprising halting the refresh counter after refreshing the row address.

19. The method of claim 16, wherein the portion of the row address comprises excluding at least the most significant bit of the row address, and wherein a wherein a count of refreshes of the row address is dependant on a count of bits of the row address included in the portion of the row address.

20. The method of claim 16, determining a number of bits to include in the portion of the row address stored at the second row address register based on a leakage severity of a digital line pair corresponding to the row address.