Data Cells with Drivers and Methods of Making and Operating the Same

• US 20130005102A1
• Filed: 09/12/2012
• Published: 01/03/2013
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 8,537,608 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

Claims

1-18. -18. (canceled)

19. A method, comprising:

forming a plurality of insulating trenches in a substrate;

forming a plurality of trench segments between the insulating trenches;

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins.

20. The method of claim 19, wherein the trench segments do not extend between more than two adjacent fins.

21. The method of claim 19, comprising forming column gates in the trench segments before forming the plurality of fins.

22. The method of claim 21, comprising forming a notch between the insulating trenches.

23. The method of claim 19, comprising forming gates adjacent sides of the plurality of fins

26. The method of claim 23 wherein forming the gates comprises depositing conductive material, followed by anisotropically etching the conductive material to remove the conductive material from horizontal surfaces and leave the conductive material adjacent sides of the plurality of fins.

27. The method of claim 19 comprising forming the plurality of trench segments and the plurality of insulating trenches to be longitudinally elongated parallel one another.

28. The method of claim 21 comprising forming gate dielectric in the trench segments before forming the plurality of fins.

29. The method of claim 19 comprising ion implanting into at least one bottom side of the plurality of trench segments to suppress formation of parasitic devices.

30. The method of claim 29 comprising ion implanting into both bottom sides of the plurality of trench segments to suppress formation of parasitic devices.

31. The method of claim 22 wherein the insulating trenches are longitudinally elongated parallel one another, the notch being longitudinally elongated perpendicular the insulating trenches.

32. The method of claim 19 wherein the trench segments are formed using multiple etching steps.

33. The method of claim 19 wherein the trench segments are longitudinally elongated, the forming of the trench segments comprising self-aligning the trench segments laterally using spacers that are laterally against insulating material projecting elevationally outward of the insulating trenches.

34. The method of claim 19 comprising conducting a threshold voltage implant into a bottom of at least one sidewall of the trench segments.

35. The method of claim 34 wherein the implant is conducted before forming the plurality of fins.

36. The method of claim 19 comprising conducting a threshold voltage implant into a bottom of opposing sidewalls of the trench segments.

37. The method of claim 36 wherein the implant is conducted before forming the plurality of fins.

24-25. -25. (canceled)

38. A method, comprising:

forming a plurality of longitudinally elongated and parallel insulating trenches in a substrate;

forming a plurality of longitudinally elongated and spaced trench segments between the insulating trenches, the trench segments extending longitudinally parallel the insulating trenches; and

forming a plurality of fins, wherein the trench segments extend between pairs of adjacent fins but not between more than four fins.