METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20130005133A1
• Filed: 06/15/2012
• Published: 01/03/2013
• Est. Priority Date: 06/28/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, JUNG-CHAN, KWAK, DAE-YOUNG, LEE, SEUNG-JAE, HUR, JAE-SUNG, KANG, SANG-BOM, JUNG, BYUNG-SUK, Zulkarnain
• Application Number:
  US13/523,928
• Publication Number:
  US 20130005133A1
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of manufacturing a semiconductor device can uniformly form a metal gate irrespective of gate pattern density. The method includes forming an interlayer dielectric layer having a trench on a substrate, forming a metal layer having first, second and third sections extending along the sides of the trench, the bottom of the trench and on the interlayer dielectric layer, respectively, forming a sacrificial layer pattern exposing an upper part of the first section of the metal layer, forming a spacer pattern on the exposed part of the first section of the metal layer, and forming a first gate metal layer by etching the first section of the metal layer using the sacrificial layer pattern and the spacer pattern as masks.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming an interlayer dielectric layer having at least one trench therein on a substrate;

subsequently forming a metal layer on the substrate such that the metal layer has a first section extending along sides of the trench, a second section extending along the bottom of the trench and a third section extending along an upper surface of the interlayer dielectric layer;

forming a sacrificial layer pattern that fills only a lower part of the trench and exposes an upper part of the first section of the metal layer in the trench;

forming a spacer pattern covering the surface of the exposed upper part of the first section of the metal layer in the trench; and

forming a first gate metal layer at the lower part of the trench by etching the metal layer using the sacrificial layer pattern and the spacer pattern together as an etch mask.

2. The method of claim 1, wherein the forming of an interlayer dielectric layer on the substrate comprises forming an interlayer dielectric layer having a first trench in a first region of the device and a second trench that is wider than the first trench in a second region device, and the first gate metal layer is formed to the same height in the first and second trenches.

3. The method of claim 1, wherein the forming of the sacrificial layer pattern comprises:

coating the substrate, on which the metal layer has been formed, with a sacrificial layer of material comprising siloxane, and

etching the sacrificial layer to expose the upper part of the first section of the metal layer.

4. The method of claim 3, wherein the sacrificial layer is etched using an etchant having an etch selectivity of 3:

1 or greater with respect to the metal layer.

5. The method of claim 1, wherein the forming of the spacer pattern comprises:

forming a spacer layer conformally along the exposed upper part of the first section of the metal layer, the sacrificial layer pattern and the interlayer dielectric film; and

removing the spacer layer from the sacrificial layer pattern and the interlayer dielectric film while leaving the spacer layer on the upper part of the first section of the metal layer.

6. The method of claim 1, wherein the forming of the spacer pattern comprises:

forming a blanket spacer layer on the substrate to such a thickness as to fill what remains of the trench; and

planarizing the spacer layer to such an extent that the third section of the metal layer is exposed.

7. The method of claim 1, wherein the spacer pattern is formed of at least one material selected from the group consisting of a silicon oxide, a silicon nitride and a carbon-based material.

8. The method of claim 1, wherein the forming of the first gate metal layer comprises:

etching the first section of the metal layer until the top thereof is disposed at the same level as or above the level of the upper surface of the second section of the metal layer, and

subsequently removing the sacrificial layer pattern and the spacer pattern.

9. The method of claim 8, wherein the sacrificial layer pattern is formed of material comprising siloxane, and the sacrificial layer pattern and the spacer pattern are removed using an etching solution of alkyl ammonium hydroxide.

10. The method of claim 1, wherein the interlayer dielectric layer is formed so as to have at least one trench therein on one region of the substrate and at least one trench therein on another region of the substrate,

the metal layer is formed in each of the trenches, and

the first gate metal layer is formed at the lower part of each of the trenches;

and

further comprising removing the first gate metal layer from each said trench on said one region of the substrate while leaving the first gate metal layer in each said trench on said another region of the substrate.

11. The method of claim 10, wherein said another region of the substrate is a PMOS region dedicated to accommodate PMOS transistors, and said one region of the substrate is an NMOS region dedicated to accommodate NMOS transistors.

12. The method of claim 1, further comprising forming a second gate metal layer that fills what remains of the trench

13. The method of claim 1, wherein the forming of the interlayer dielectric layer comprises:

forming a dummy gate pattern on the substrate,

forming dielectric material on the substrate on which the dummy gate pattern is disposed, and

subsequently removing the dummy gate pattern.

14. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming an interlayer dielectric layer having at least one first trench therein on one region of the substrate and at least one second trench therein on another region on the substrate;

forming a mask layer that covers said another region of the substrate;

forming a metal layer in each said at least one first trench, wherein the metal layer has a first section extending along the sides of each said first trench and a second section extending along the bottom of each said first trench;

forming a sacrificial layer pattern that fills only a lower part of each said first trench and exposes an upper part of the first section of the metal layer in the first trench;

forming a spacer pattern covering the surface of the exposed upper part of the first section of the metal layer in each said first trench;

forming a first gate metal layer at the lower part of each said first trench by etching the metal layer using the sacrificial layer and spacer patterns together as an etch mask;

removing the mask layer; and

subsequently forming a second gate metal layer that fills what remains of each said first trench and that fills each said second trench.

15. The method of claim 14, wherein the at least one first trench comprises one trench having a first width and another trench having a second width different from the first width, and the first metal layer is formed so as to have the same height in the trenches having the first and second widths different from each other.

16. A method of manufacturing a semiconductor device, the method comprising:

forming an interlayer dielectric layer having first and second trenches therein on a substrate;

subsequently forming a metal layer on the substrate conforming to the underlying topography of an intermediate structure that includes the interlayer dielectric layer and the first and second trenches, whereby the metal layer extends along surfaces delimiting the sides and bottoms of the first and second trenches;

subsequently forming a sacrificial layer pattern on the substrate by a process that results in the filling of the first trench with sacrificial material to a first level and the filling of the second trench with sacrificial material to a second level below the first level, such that the sacrificial layer pattern formed of said sacrificial material exposes more of the metal layer in the second trench than in the first trench;

forming a spacer pattern that covers those parts of the metal layer exposed by the sacrificial layer pattern; and

forming a first gate metal layer at the lower part of each of the first and second trenches by etching the metal layer using the sacrificial layer and spacer patterns together as an etch mask.

17. The method of claim 16, wherein the forming of the sacrificial layer pattern comprises:

depositing sacrificial material comprising siloxane on the substrate to form a sacrificial layer that is thicker at the location of the first trench than at the location of the second trench, and

etching the sacrificial layer.

18. The method of claim 16, wherein the spacer pattern is formed of at least one material selected from the group consisting of a silicon oxide, a silicon nitride and a carbon-based material.

19. The method of claim 16, wherein the first trench is narrower than the second trench, and

the forming of the first gate metal layer comprises etching the metal layer until the top thereof is disposed at the same level in each of the first and second trenches, and subsequently removing the sacrificial layer and spacer patterns;

and

further comprising filling what remains of the first and second trenches with a second gate metal layer.

20. The method of claim 16, wherein the spacer pattern is formed of at least one material selected from the group consisting of a silicon oxide, a silicon nitride and a carbon-based material, the sacrificial layer pattern is formed of material comprising siloxane, and the sacrificial layer and spacer patterns are removed using an etching solution of alkyl ammonium hydroxide.