METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED INTEGRATED CIRCUITS

• US 20130006557A1
• Filed: 06/29/2011
• Published: 01/03/2013
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: Duke University
• Original Assignee: Duke University
• Inventors: Chakrabarty, Krishnendu, Noia, Brandon
• Granted Patent: US 8,775,108 B2
• Time in Patent Office: Days
• US Class Current: 702/65
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a “floated state” or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.

Claims

1. An on-chip architecture for through-silicon-via (TSV) testing, comprising:

a scan flop receiving a clock signal input, a test input, a functional input, and a test select input; and

providing a first signal at an output node; and

an open signal controlled gate element at the output node of the scan flop, the gate element receiving the first signal from the scan flop and providing a Q output, wherein the gate element receives the open signal to control whether the Q output is floating or takes a value of the first signal.

2. The on-chip architecture for TSV testing according to claim 1, wherein each TSV of a die having the on-chip architecture for TSV testing is connected to receive a corresponding Q output.

3. The on-chip architecture for TSV testing according to claim 1, wherein the gate element comprises a transmission gate.

4. The on-chip architecture for TSV testing according to claim 3, further comprising an output buffer between the output node of the scan flop and the transmission gate.

5. The on-chip architecture for TSV testing according to claim 1, wherein the gate element comprises a tri-state buffer, wherein a control input of the tri-state buffer receives the open signal.

6. The on-chip architecture for TSV testing according to claim 1, wherein the scan flop comprises:

a MUX receiving the test input, the functional input, and the test select input;

a first transmission gate passing an output of the MUX to a first delay stage according to the clock signal;

the first delay stage comprising a first cross coupled inverter pair;

a second transmission gate passing a value stored in the first delay stage to a second delay stage according to the clock signal; and

the second delay stage comprising a second cross coupled inverter pair, wherein the gate element is connected to receive the first signal from the second delay stage.

7. The on-chip architecture for TSV testing according to claim 6, wherein widths of transistors in the first cross-coupled inverter pair are greater than those of transistors in the second cross-coupled inverter pair.

8. The on-chip architecture for TSV testing according to claim 1, further comprising a controller configured to output the open signal to the gate element.

9. The on-chip architecture for TSV testing according to claim 8, wherein the controller is further configured to output the open signal to the gate element for each open signal controlled gate element of a TSV matrix, wherein a TSV matrix comprises a number of TSVs that can be contacted by a single probe needle, each of the TSVs being connected to receive a corresponding Q output via the open signal controlled gate element.

10. The on-chip architecture for TSV testing according to claim 9, wherein the controller comprises a synchronous up-counter connected to a decoder directing the open signal to a particular gate element connected to the TSV matrix.

11. A method of pre-bond testing of TSVs of a stacked integrated circuit using the on-chip architecture for TSV testing according to claim 1, the method comprising:

contacting a probe card comprising a first plurality of probe needles to a die under test (DUT), wherein each probe needle comprises an active driver, the active driver being configured to monitor a capacitance, charge the capacitance to a known voltage, and controllably connect and disconnect the capacitance from the probe needle,

wherein each probe needle of the first plurality of probe needles contacts a corresponding TSV matrix, wherein each TSV of the corresponding TSV matrix is connected to receive the Q output from a corresponding one gate element; and

performing a test on the contacted TSV matrices.

12. The method according to claim 11, wherein the probe card further comprises a second plurality of probe needles, the probe needles of the second plurality being configured to connect to signal pads on the DUT.

13. The method according to claim 11, wherein the probe card comprises a checkerboard configuration for the first plurality of probe needles, wherein the method further comprises:

after testing the TSV matrices contacted by the plurality of probe needles, lifting the probe card and shifting the probe card by an offset amount in order to contact untested TSV matrices; and

performing the test on the untested TSV matrices.

14. The method according to claim 13, wherein performing the test comprises determining capacitance of the TSVs of the DUT by performing the sequential steps of:

a) charging the capacitance to the known voltage, applying a first test value to the test input for each scan flop, and applying an open value as the open signal to each gate element;

b) applying a close value as the open signal to each gate element, stopping the charging of the capacitance to the known voltage, and connecting the charged capacitance to each probe needle to allow charge sharing between the contacted TSVs and the charged capacitance; and

c) measuring a voltage across the charged capacitance after a predetermined period of time.

15. The method according to claim 14, further comprising:

d) determining each TSV'"'"'s capacitance by;

calculating

16. The method according to claim 13, wherein performing the test comprises determining resistance of the TSVs of the DUT by performing the sequential steps of:

a) applying a second test value to the test input for each scan flop, applying a close value as the open signal to each gate element, connecting the capacitance to each probe needle, and discharging all TSVs and the capacitance;

b) applying an open value as the open signal to at least one gate element for each TSV matrix, thereby allowing the connected capacitance to be charged by the TSV having the gate element with the applied open value

c) monitoring a voltage across the capacitance, and recording a time to charge the capacitance to a predetermined voltage;

d) comparing the recorded time to a calibrated charge curve of a non-faulty TSV; and

e) performing steps (a)-(d) for each remaining TSV in the TSV matrices.

17. The method according to claim 16, wherein applying the open value as the open signal to the at least one gate element for each TSV matrix is performed for one TSV at a time.

18. The method according to claim 16, wherein applying the open value as the open signal to the at least one gate element for each TSV matrix is performed for two or three TSVs at a time.