Parameter Tracking for Memory Devices

• US 20130007343A1
• Filed: 06/28/2011
• Published: 01/03/2013
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Rub, Bernardo, Patapoutian, Ara, Buch, Bruce
• Granted Patent: US 8,745,318 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device.

Claims

1. A method of operating a controller for a charge storage memory device, comprising:

monitoring a set of first parameters of at least one of the memory units of the memory device, the set of first parameters associated with wear of the memory device and the monitoring including measuring the first parameters at each of multiple first intervals that occur over a time period that the memory device is in operation;

comparing the first parameters to respective trigger criterion;

in response to the comparing, triggering collection of a set of second parameters associated with wear of the memory device; and

developing memory wear information using the second parameters.

2. The method of claim 1, wherein the set of first parameters overlaps the set of second parameters.

3. The method of claim 1, wherein the memory wear information comprises channel configuration information used to configure a read/write channel of the memory device to compensate for wear of the memory device.

4. The method of claim 1, wherein the memory device comprises blocks of memory units and the first intervals are timed according to block-level memory device operations.

5. The method of claim 4, wherein:

the blocks of the memory units are garbage collection units; and

the block level memory device operations are garbage collection operations.

6. The method of claim 4, further comprising storing at least one of the first parameters and the second parameters for each block of memory units in a storage area within the block of memory units.

7. The method of claim 6, further comprising:

moving the first and second parameters stored in the storage area to a temporary storage location while a block level operation is being performed on the block of memory units;

measuring a current set of second parameters;

updating the set of second parameters using the current set of second parameters; and

storing the updated set of second parameters in the storage area after the block-level memory device operation has been performed on the block of memory units.

8. The method of claim 1, wherein:

monitoring the set of first parameters of the at least one memory unit comprises monitoring the set of first parameters for multiple memory units of a block and combining the first parameters of the multiple memory units to form one or more block level first parameters; and

comparing the first parameters to respective trigger criterion comprises comparing the block level first parameters to respective block level trigger criterion.

9. The method of claim 1, further comprising forming a historical profile using the set of second parameters.

10. The method of claim 1, wherein the memory wear information comprises memory lifetime information.

11. A controller for a memory device, comprising:

a block level operation module configured to perform block level operations on multiple memory blocks, each memory block comprising multiple memory units;

a parameter control module configured to, for each memory block;

monitor a set of first parameters associated with wear of at least one memory unit of the memory block by measuring the set of first parameters during each block level operation;

compare the first parameters to respective trigger criterion; and

in response to the comparison, trigger collection of a set of second parameters associated with wear of the memory block; and

a channel control module configured to develop memory wear information using the set of second parameters.

12. The device of claim 11, wherein the memory device comprises a flash memory device.

13. The device of claim 11, wherein monitoring the set of first parameters involves less system overhead than collecting the set of second parameters.

14. The device of claim 11, wherein:

the at least one memory unit comprises a memory unit having a higher wear rate than other memory units of the memory block

15. The device of claim 11, wherein each memory block includes a storage area and second parameters for each memory block are stored in the storage area of the memory block.

16. The device of claim 11, wherein:

the memory device comprises multilevel memory cells capable of storing a most significant bit (MSB) and a least significant bit (LSB); and

the parameter control module is configured to measure the set of second parameters for a memory unit of MSBs and to measure the set of second parameters for a memory unit of LSBs and to aggregate the set of second parameters for the MSB memory unit and the set of second parameters for the LSB memory unit into an aggregate set of second parameters, wherein the MSB memory unit and the LSB memory unit are stored together in one physical memory unit.

17. The device of claim 11, wherein the parameter control module is configured to increase a frequency at which the set of second parameters is collected based on the set of first parameters.

18. A controller for a memory device, comprising:

a block level operation module configured to perform block level operations on a memory block comprising multiple memory units;

a parameter control module configured to, for each memory block;

monitor a set of first parameters associated with wear of at least one memory unit of the memory block by measuring the set of first parameters of the at least one memory unit during block level operations;

compare the first parameters to respective trigger criterion; and

in response to the comparison, trigger collection of a set of second parameters associated with wear of the memory block, wherein collection of the set of second parameters includes measuring the second parameters during block level operations; and

a read/write channel control module configured to develop channel configuration information that compensates for memory wear using the set of second parameters and to use the channel configuration information to configure a read/write channel to access the memory units of the memory block.

19. The device of claim 18, wherein the channel configuration is stored in a temporary location and the read/write channel control module is configured to use the channel configuration information stored in the temporary location to configure the read/write channel for on-the-fly read operations.

20. The device of claim 18, wherein the r channel configuration information is stored in a temporary location and the read/write channel control module is configured to use the channel configuration information stored in the temporary location to configure the read/write channel for sequential write operations of the multiple memory units of the memory block.