ESTIMATING TEMPORAL DEGRADATION OF NON-VOLATILE SOLID-STATE MEMORY

• US 20130007543A1
• Filed: 06/30/2011
• Published: 01/03/2013
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Goss, Ryan James, Seekins, David Scott, Gaertner, Mark Allen
• Granted Patent: US 8,645,773 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/50016 of retention

Abstract

Representative locations of a non-volatile, solid-state memory of an apparatus store characterization data. An event during which elapsed time is not measured by the apparatus is determined. In response to the event, temporal degradation of the non-volatile, solid-state memory during the event is estimated based on electrical characteristics of the representative locations.

Claims

1. A method comprising:

identifying representative locations of a non-volatile, solid-state memory of an apparatus that store characterization data;

detecting an event during which elapsed time is not measured by the apparatus; and

in response to the event, estimating temporal degradation of the non-volatile, solid-state memory during the event based on electrical characteristics of the representative locations.

2. The method of claim 1, further comprising performing a data recovery operation on the non-volatile, solid-state memory that includes at least one of a voltage shift and an iterative correction, wherein the estimated temporal degradation facilitates performing the data recovery operation.

3. The method of claim 2, further comprising determining a plurality of temporal degradations each based on the electrical characteristics locations within respective divisions of the non-volatile, solid-state memory, wherein the data recovery operations are tailored for the divisions based on the respective temporal degradations.

4. The method of claim 1, wherein the electrical characteristics of the representative locations comprise at least one of bit error rate and a voltage shift.

5. The method of claim 1, wherein the event comprises a power off event.

6. The method of claim 1, further comprising performing a data refresh operation on one or more portions of the non-volatile, solid-state memory based on the estimated temporal degradation satisfying a threshold value.

7. The method of claim 1, wherein the representative locations are randomly chosen.

8. The method of claim 1, wherein the representative locations are predetermined locations that exhibit distinct characterization information.

9. The method of claim 1, wherein the characterization data stored at the representative locations comprise at least one of:

a known signature pattern; and

user data with an extra amount of error correction code.

10. An apparatus comprising:

a controller capable of being coupled to a non-volatile, solid-state memory, and configured to;

identify representative locations of the non-volatile, solid-state memory;

detect an event during which elapsed time is not measured by the apparatus; and

in response to the event, estimate temporal degradation of the non-volatile, solid-state memory during the event based on electrical characteristics of the representative locations.

11. The apparatus of claim 10, wherein the controller is further configured to perform a data recovery operation on the non-volatile, solid-state memory that includes at least one of voltage shift and an iterative correction, wherein the estimated temporal degradation facilitates performing the data recovery operation.

12. The apparatus of claim 11, wherein the controller is further configured to determine a plurality of temporal degradations each based on the electrical characteristics of locations within respective divisions of the non-volatile, solid-state memory, wherein the data recovery operations are tailored for the divisions based on the respective temporal degradations.

13. The apparatus of claim 10, wherein the electrical characteristics of the representative locations comprise at least one of bit error rate and a voltage shift.

14. The apparatus of claim 10, wherein the event comprises a power off event.

15. The apparatus of claim 10, further comprising performing a data refresh operation on one or more portions of the non-volatile, solid-state memory based on the estimated temporal degradation satisfying a threshold value.

16. The apparatus of claim 10, wherein the representative locations are randomly chosen.

17. The apparatus of claim 10, wherein the representative locations are predetermined locations that exhibit distinct characterization information.

18. The apparatus of claim 10, wherein data stored at the representative locations comprise at least one of:

a known signature pattern; and

user data with an extra amount of error correction code.

19. An apparatus comprising:

a controller capable of being coupled to a non-volatile, solid-state memory, and configured to;

detect an event during which elapsed time is not measured by the apparatus;

in response to the event, recover characterization data at representative locations of the non-volatile, solid-state memory to determine electrical characteristics of the representative locations; and

estimate temporal degradation of the non-volatile, solid-state memory during the event based on the electrical characteristics.

20. The apparatus of claim 20, wherein the characterization data comprise at least one of:

a known signature pattern; and

user data with an extra amount of error correction code.