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AUTOMATED INLINE DEFECT CHARACTERIZATION

  • US 20130007684A1
  • Filed: 06/29/2012
  • Published: 01/03/2013
  • Est. Priority Date: 06/30/2011
  • Status: Active Grant
First Claim
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1. A computer implemented method for performing defect characterization comprising:

  • importing a layout for a semiconductor circuit;

    importing a netlist for the semiconductor circuit;

    obtaining images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

    detecting a defect in one of the images of the semiconductor chip wherein the defect is at a location on a portion the semiconductor chip that is represented by the layout; and

    performing electrical analysis of the netlist with the defect which was detected.

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