AUTOMATED INLINE DEFECT CHARACTERIZATION

• US 20130007684A1
• Filed: 06/29/2012
• Published: 01/03/2013
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Oberai, Ankush, Kramer, James Robert
• Granted Patent: US 8,826,209 B2
• Time in Patent Office: Days
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Defect characterization is a useful tool for analyzing and improving fabrication for semiconductor chips. By using layout and netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, performance, and other characteristics.

Claims

1. A computer implemented method for performing defect characterization comprising:

importing a layout for a semiconductor circuit;

importing a netlist for the semiconductor circuit;

obtaining images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

detecting a defect in one of the images of the semiconductor chip wherein the defect is at a location on a portion the semiconductor chip that is represented by the layout; and

performing electrical analysis of the netlist with the defect which was detected.

2. The method according to claim 1 wherein the detecting the defect is accomplished inline during semiconductor manufacturing.

3. The method according to claim 1 further comprising importing a schematic for the semiconductor circuit.

4. The method according to claim 3 further comprising cross mapping between two of a group comprising the netlist, the schematic, and the layout.

5. The method according to claim 1 wherein the defect is detected using one of a group comprising an optical microscope and a scanning electronic microscope.

6. The method according to claim 1 wherein the defect is emphasized using voltage contrast.

7. The method according to claim 1 further comprising identifying an intersection of nets based on a failure of electrical operation.

8. The method according to claim 7 wherein the obtaining of the images is based on the intersection of the nets which were identified.

9. The method according to claim 1 further comprising determining a critical dimension.

10. The method according to claim 9 further comprising filtering out defects smaller than the critical dimension.

11. The method according to claim 9 wherein the critical dimension is between shapes on a single level.

12. The method according to claim 1 further comprising determining a critical volume.

13. The method according to claim 12 further comprising filtering out defects smaller than the critical volume.

14. The method according to claim 12 wherein the critical volume is between shapes on a plurality of levels.

15. The method according to claim 1 further comprising ranking the defect and a second defect based on their impact to operation of the semiconductor circuit.

16. The method according to claim 1 further comprising using an uncertainty value for the location to determine a range of possible defect locations.

17. The method according to claim 16 further comprising analyzing the possible defect locations for impact to operation of the semiconductor circuit.

18. The method according to claim 1 further comprising determining a cell in the semiconductor circuit in which the defect resides.

19. The method according to claim 18 further comprising extracting nets from the cell.

26. The method according to claim 1 further comprising correlating an impact of the defect on electrical operation of the semiconductor circuit.

27. The method according to claim 26 wherein the correlating relates to one of a group comprising yield analysis, parametric information, fabrication process data, and circuit speed.

28. The method according to claim 1 further comprising classifying the defect which was detected.

29. The method according to claim 1 wherein the electrical analysis of the netlist with the defect is performed using transistor level simulation.

30. The method according to claim 29 wherein the transistor level simulation includes Monte Carlo analysis.

31. The method according to claim 1 further comprising searching through the layout for similar geometries to the layout of the portion of the semiconductor chip where the defect was detected.

32. The method according to claim 31 wherein one or more additional defects are detected on the similar geometries.

33. The method according to claim 31 further comprising performing categorical binning of the similar geometries.

34. The method according to claim 1 further comprising producing a series of modulated lithography exposures;

examining shapes produced by the series of modulated lithography exposures; and

identifying marginal structures where a similar defect to the defect that was detected would impact circuit operation based on the series of modulated lithography exposures.

40. The method according to claim 1 further comprising providing CAD navigation on the semiconductor chip to the location where the defect was detected.

20-25. -25. (canceled)

35-39. -39. (canceled)

41. A computer program product embodied in a non-transitory computer readable medium for defect characterization, the computer program product comprising:

code for importing a layout for a semiconductor circuit;

code for importing a netlist for the semiconductor circuit;

code for obtaining images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

code for detecting a defect in one of the images of the semiconductor chip wherein the defect is at a location on a portion the semiconductor chip that is represented by the layout; and

code for performing electrical analysis of the netlist with the defect which was detected.

42. A computer system for defect characterization comprising:

a memory for storing instructions;

one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to;

import a layout for a semiconductor circuit;

import a netlist for the semiconductor circuit;

obtain images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

detect a defect in one of the images of the semiconductor chip wherein the defect is at a location on a portion the semiconductor chip that is represented by the layout; and

perform electrical analysis of the netlist with the defect which was detected.

43. A computer program product embodied in a non-transitory computer readable medium for defect characterization, the computer program product comprising:

code for importing a layout for a semiconductor circuit;

code for importing a netlist for the semiconductor circuit;

code for obtaining images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

code for detecting a defect larger than a critical dimension in one of the images of the semiconductor chip; and

code for performing electrical analysis of the netlist with the detected defect.