Method for Efficiently Fabricating Memory Cells with Logic FETs and Related Structure

• US 20130009231A1
• Filed: 07/08/2011
• Published: 01/10/2013
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Xia, Wei, Chen, Xiangdong
• Granted Patent: US 9,129,856 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

Claims

1. A method for concurrently fabricating a memory region with a logic region in a common substrate, said method comprising:

forming a lower dielectric segment in said common substrate in said memory and logic regions;

forming a polysilicon segment over said lower dielectric segment in said memory region, while concurrently forming a sacrificial polysilicon segment over said lower dielectric segment in said logic region;

removing from said logic region said lower dielectric segment and said sacrificial polysilicon segment;

forming a high-k segment in said logic region over said common substrate;

forming a metal segment over said high-k segment said logic region.

2. The method of claim 1, wherein said forming said high-k segment in said logic region includes forming another high-k segment in said memory region over said polysilicon segment;

and

wherein said forming said metal segment in said logic region includes forming another metal segment over said another high-k segment in said memory region.

3. The method of claim 1, wherein said polysilicon segment is a floating gate of a memory cell in said memory region.

4. The method of claim 1, wherein said lower dielectric segment in said memory region is a floating gate dielectric of a memory cell in said memory region.

5. The method of claim 1, wherein said high-k segment is a transistor gate dielectric of a logic field-effect transistor (FET), and said metal segment is a metal gate of said logic FET.

6. The method of claim 1 further comprising forming spacers adjacent to said polysilicon segment and adjacent to said sacrificial polysilicon segment.

7. The method of claim 1 further comprising forming a source/drain region adjacent to said polysilicon segment in said memory region and adjacent to said sacrificial polysilicon segment in said logic region.

8. The method of claim 1 further comprising forming a cap segment over said polysilicon segment in said memory region and over said sacrificial polysilicon segment in said logic region thereby preventing silicidation of said polysilicon segment and said sacrificial polysilicon segment.

9. A method for concurrently fabricating a memory region with a logic region in a common substrate, said method comprising:

forming a lower dielectric segment in said common substrate in said memory and logic regions;

forming a polysilicon segment over said lower dielectric segment in said memory region, while concurrently forming a sacrificial polysilicon segment over said lower dielectric segment in said logic region;

removing from said logic region said lower dielectric segment and said sacrificial polysilicon segment;

forming a high-k segment in said logic region over said common substrate, and in said memory region over said polysilicon segment;

forming a metal segment over said high-k segment in said logic and memory regions.

10. The method of claim 9, wherein said polysilicon segment is a floating gate of a memory cell in said memory region, and said metal segment in said memory region is a control gate of said memory cell.

11. The method of claim 9, wherein said high-k segment in said memory region is a control gate dielectric of a memory cell in said memory region.

12. A semiconductor die comprising a memory region concurrently fabricated with a logic region in a common substrate;

said memory region including a memory cell having a metal segment over a high-k segment over a polysilicon segment situated over a lower dielectric segment in said common substrate;

said logic region including a logic FET having a metal gate over a transistor gate dielectric in said common substrate, wherein a sacrificial poly segment and another lower dielectric segment have been removed from said logic region, and wherein said metal gate and said metal segment are formed from a metal layer, and said transistor gate dielectric and said high-k segment are formed from a high-k layer.

13. The semiconductor die of claim 12, wherein said polysilicon segment is a floating gate of said memory cell, and said metal segment is a control gate of said memory cell.

14. The semiconductor die of claim 12, wherein said lower dielectric segment is a floating gate dielectric of said memory cell.

15. The semiconductor die of claim 12, wherein said high-k segment is a control gate dielectric of said memory cell.

16. The semiconductor die of claim 12, wherein said lower dielectric segment comprises an oxide.

17. The semiconductor die of claim 12, where said high-k segment is selected from the group consisting of hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and chromium oxide (CrO₂).

18. The semiconductor die of claim 12, wherein said metal layer is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).

19. The semiconductor die of claim 12, wherein said memory cell and said logic FET are within an interlayer dielectric, said interlayer dielectric comprising a nitride.

20. The semiconductor die of claim 12, wherein said memory cell and said logic FET each comprises a source/drain region and a silicide segment formed on said source/drain region.