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UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS

  • US 20130009324A1
  • Filed: 09/14/2012
  • Published: 01/10/2013
  • Est. Priority Date: 04/28/2009
  • Status: Active Grant
First Claim
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1. A circuit arrangement, comprising:

  • a plurality of semiconductor dies physically and electrically coupled to one another in a stack, each semiconductor die including opposing faces, wherein at least one face of each semiconductor die includes circuit logic integrated thereon and defining a circuit layer that includes at least one functional unit, wherein at least one face of each semiconductor die includes a standardized inter-layer interface region disposed thereon, and wherein each inter-layer interface region on each semiconductor die is disposed at substantially the same topographic location when the respective semiconductor die is disposed within the stack; and

    a standardized inter-layer bus electrically coupling the functional units on the plurality of semiconductor dies to one another, the inter-layer bus comprising a plurality of electrical conductors disposed within the inter-layer interface region of each semiconductor die and extending between the opposing faces of each semiconductor die, wherein respective electrical conductors disposed in the inter-layer interface regions of adjacent semiconductor dies in the stack are electrically coupled to one another when the plurality of circuit layers are physically and electrically coupled to one another in the stack.

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