SEMICONDUCTOR ELEMENT-EMBEDDED SUBSTRATE, AND METHOD OF MANUFACTURING THE SUBSTRATE

• US 20130009325A1
• Filed: 01/25/2011
• Published: 01/10/2013
• Est. Priority Date: 03/18/2010
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Mori, Kentaro, Yamamichi, Shintaro, Murai, Hideya, Kikuchi, Katsumi, Nakashima, Yoshiki, Ohshima, Daisuke
• Granted Patent: US 8,810,008 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/187 : the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line;

and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Claims

1. A semiconductor element-embedded substrate comprising:

a semiconductor element;

a chip component;

a peripheral insulating layer covering at least outer circumferential side surfaces of the semiconductor element and the chip component;

an upper surface-side wiring line provided on the upper surface side of the wiring substrate; and

a lower surface-side wiring line provided on the lower surface side of the wing substrate,

wherein the semiconductor element comprises a terminal on the upper surface side thereof, the terminal being electrically connected to the upper surface-side wiring line, and

the chip component comprises;

an upper surface-side terminal electrically connected to the upper surface-side wiring line;

a lower surface-side terminal electrically connected to the lower surface-side wiring line; and

a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

2. The semiconductor element-embedded substrate according to claim 1, wherein the semiconductor element is a semiconductor chip including a semiconductor circuit, and the chip component is a semiconductor chip not including any semiconductor circuits.

3. The semiconductor element-embedded substrate according to claim 1, wherein the planar area of the chip component is larger than the planar area of the semiconductor element.

4. The semiconductor element-embedded substrate according to claim 1, wherein a plurality of the chip components is disposed so as to surround the outer circumferential side surfaces of the semiconductor element.

5. The semiconductor element-embedded substrate according to claim 1, wherein the terminal of the semiconductor element is connected to the upper surface-side wiring line through a via,

the upper surface-side terminal of the chip component is connected to the upper surface-side wiring line through a via, and

the lower surface-side terminal of the chip component is connected to the lower surface-side wiring line through a via.

6. The semiconductor element-embedded substrate according to claim 1, wherein the terminal of the semiconductor element is connected to the upper surface-side wiring line through a via,

the upper surface-side terminal of the chip component is connected to the upper surface-side wiring line through a via, and

the lower surface-side terminal of the chip component is connected to the lower surface-side wiring line through a solder member.

7. The semiconductor element-embedded substrate according to claim 1, wherein the peripheral insulating layer comprises a lower surface-side insulating layer for covering the lower surface of the semiconductor element and the lower surface of the chip component;

a reinforcing insulating layer for surrounding the outer circumferential side surfaces of the semiconductor element and the outer circumferential side surfaces of the chip component; and

an upper surface-side insulating layer for covering the upper surface of the semiconductor element and the upper surface of the chip component.

8. The semiconductor element-embedded substrate according to claim 1, wherein a lateral-to-chip via penetrating through the peripheral insulating layer is provided in a region around the semiconductor element and the chip component.

9. The semiconductor element-embedded substrate according to claim 8, wherein the outer diameter of the lateral-to-chip via is larger than the outer diameter of the through-chip via.

10. The semiconductor element-embedded substrate according to claim 9, wherein power or ground is applied through the lateral-to-chip via and a signal is conducted through the through-chip via.

11. The semiconductor element-embedded substrate according to claim 1, further comprising a protective insulating film for covering the upper surface-side wiring line, the protective insulating film having an opening;

and an external terminal formed of an exposed portion of the upper surface-side wiring line within the opening, or an external terminal formed of a conductive part provided in the opening.

12. The semiconductor element-embedded substrate according to claim 1, further comprising a multilayer interconnection structure comprising wiring lines and insulating layers alternately provided on the upper surface side of the substrate.

13. The semiconductor element-embedded substrate according to claim 12, further comprising an insulating film having an opening on the uppermost layer side of the multilayer interconnection structure on the upper surface side;

and an external terminal formed of an exposed portion of a wiring line within the opening, or an external terminal formed of a conductive part provided in the opening.

14. The semiconductor element-embedded substrate according to claim 1, further comprising a multilayer interconnection structure comprising wiring lines and insulating layers alternately provided on the lower surface side of the substrate.

15. The semiconductor element-embedded substrate according to claim 14, further comprising an insulating film having an opening on the lowermost layer side of the multilayer interconnection structure on the lower surface side;

and an external terminal formed of an exposed portion of a wiring line within the opening, or an external terminal formed of a conductive part provided in the opening.

16. The semiconductor element-embedded substrate according to claim 1, further comprising a protective insulating film for covering the lower surface-side wiring line, the protective insulating film having an opening;

and an external terminal formed of an exposed portion of the lower surface-side wiring line within the opening, or an external terminal formed of a conductive part provided in the opening.

17. A method of manufacturing a wiring substrate comprising a semiconductor element built therein, the method comprising:

mounting a semiconductor element including a terminal on the upper surface side thereof on a support medium with the lower surface of the semiconductor element facing the support medium side;

mounting a chip component including terminals on the upper surface side and the lower surface side thereof on the support medium;

forming a peripheral insulating layer for covering the semiconductor element and the chip component;

removing the support medium;

forming a first wiring line for electrical connection with the lower surface-side terminal of the chip component; and

forming a second wiring line for electrical connection with the terminal of the semiconductor element and the upper surface-side terminal of the chip component,

wherein the chip component includes a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

18. The manufacturing method according to claim 17, further comprising forming a foundation insulating layer on the support medium, wherein the semiconductor element and the chip component are mounted on the foundation insulating layer.

19. The manufacturing method according to claim 17, wherein the semiconductor element and the chip component are respectively mounted through adhesion layers.

23. The manufacturing method according to claim 17, wherein the peripheral insulating layer comprises a first insulating layer surrounding the outer circumferential side surfaces of the semiconductor element and the chip component;

and a second insulating layer covering the upper surfaces of the semiconductor element and the chip component.

24. The manufacturing method according to claim 23, wherein the first insulating layer includes a reinforcing material.

20. A method of manufacturing a wiring substrate comprising a semiconductor element built therein, the method comprising:

forming at least a first wiring line on a support medium;

mounting a semiconductor element including a terminal on the upper surface side thereof on the support medium with the lower surface of the semiconductor element facing the support medium side;

mounting a chip component including terminals on the upper surface side and the lower surface side thereof on the support medium, such that the lower surface-side terminal is electrically connected to the first wiring line;

forming a peripheral insulating layer for covering the semiconductor element and the chip component;

removing the support medium; and

forming a second wiring line for electrical connection with the terminal of the semiconductor element and the upper surface-side terminal of the chip component,

wherein the chip component includes a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

21. The manufacturing method according to claim 20, wherein a multilayer interconnection structure including the first wiring line as an uppermost layer-side wiring line and including wiring lines and insulating layers alternately provided on the support medium is formed in the formation of the first wiring line,

the semiconductor element and the chip component are mounted on the multilayer interconnection structure, and

the lower surface-side terminal of the chip component is electrically connected to the first wiring line.

22. The manufacturing method according to claim 20, wherein the lower surface-side terminal of the chip component is connected to the first wiring line through a solder member.

25. The manufacturing method according to claim 20, wherein the peripheral insulating layer comprises a first insulating layer surrounding the outer circumferential side surfaces of the semiconductor element and the chip component;

and a second insulating layer covering the upper surfaces of the semiconductor element and the chip component.

26. The manufacturing method according to claim 25, wherein the first insulating layer includes a reinforcing material.