Integrated Circuit Elementary Cell with a Low Sensitivity to External Disturbances
First Claim
1. An integrated electronic circuit comprising elements implementing a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements, said means for attenuating configured to receive a writing activating signal indicating said phases of intentional modification of the state of the elements.
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Accused Products
Abstract
The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.
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Citations
24 Claims
- 1. An integrated electronic circuit comprising elements implementing a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements, said means for attenuating configured to receive a writing activating signal indicating said phases of intentional modification of the state of the elements.
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12. A circuit comprising:
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a logic circuit having an output, the output configured to have a first state and a second state; and an attenuator circuit coupled to the output, the attenuator circuit configured to operate in a first mode that resists a change in state of the output and a second mode that does not resist a change in state of the output. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. An integrated-circuit comprising:
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at least one logic circuit, the logic circuit having an input node and an output node, the output node configured to have a first state and a second state; at least one attenuator circuit associated with the at least one logic circuit and coupled to the output of the at least one logic circuit, the at least one attenuator circuit having an activation signal input;
whereinthe at least one attenuator circuit configured to, in response to a first activation signal, resist a change in state of the output of the logic device, and in response to a second activation signal, not resist a change in state of the output of the logic device. - View Dependent Claims (20, 21, 22, 23)
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Specification