SEMICONDUCTOR APPARATUS AND SYSTEM

• US 20130009684A1
• Filed: 07/06/2012
• Published: 01/10/2013
• Est. Priority Date: 07/06/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Mobile Corporation (Renesas Electronics Corporation)
• Inventors: Fujigaya, Masaki, Irita, Takahiro
• Granted Patent: US 9,176,568 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Claims

1. A semiconductor apparatus comprising;

a circuit including a predetermined function;

a clock generating circuit that generates a clock signal supplied to the circuit;

a clock control circuit that controls the clock generating circuit; and

a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit.

2. The semiconductor apparatus according to claim 1, wherein a power supply voltage to be supplied to the circuit is adjusted according to the notification signal.

3. The semiconductor apparatus according to claim 1, further comprising a power control circuit that controls power supplied to the circuit,

wherein the notification signal generating circuit notifies a timing for the power control circuit to perform control.

4. The semiconductor apparatus according to claim 1, wherein the notification signal is a signal for notifying that an operating current of the circuit increases.

5. The semiconductor apparatus according to claim 1, wherein the notification signal generating circuit generates the notification signal when the clock control circuit controls the clock generating circuit so that a frequency of the clock signal supplied to the circuit will be higher than a predetermined frequency.

6. The semiconductor apparatus according to claim 1, wherein the notification signal generating circuit generates the notification signal when the clock control circuit controls the clock generating circuit so that the clock signal is supplied to the circuit.

7. The semiconductor apparatus according to claim 3, wherein the notification signal generating circuit generates the notification signal when the power control circuit controls the circuit so that the power is supplied to the circuit.

8. The semiconductor apparatus according to claim 3, wherein the notification signal generating circuit generates the notification signal at not less than one of a timing when the clock control circuit controls the clock generating circuit so that the clock signal is supplied to the circuit and a timing when the power control circuit controls the circuit so that the power is supplied to the circuit.

9. The semiconductor apparatus according to claim 1, wherein

the clock control circuit comprises a first state machine, and

the notification signal generating circuit generates the notification signal according to a state of the first state machine.

10. The semiconductor apparatus according to claim 9, wherein the notification signal generating circuit generates the notification signal in a period when the first state machine performs a process to increase a frequency of the clock signal supplied to the circuit to be higher than a predetermined frequency.

11. The semiconductor apparatus according to claim 9, wherein the notification signal generating circuit generates the notification signal in a period when the first state machine performs a process to supply the clock signal to the circuit.

12. The semiconductor apparatus according to claim 3, wherein

the power control circuit comprises a second state machine, and

the notification signal generating circuit generates the notification signal according to a state of the second state machine.

13. The semiconductor apparatus according to claim 12, wherein the notification signal generating circuit generates the notification signal in a period when the second state machine performs a process to supply the power to the circuit.

14. The semiconductor apparatus according to claim 1, wherein

the circuit comprises a processor including a CPU and a cache memory and a memory access detecting unit that detects the number of accesses to the cache memory by the CPU and calculates an expected amount of current consumption in the processor according to the number of accesses, and

the clock control circuit controls the clock generating circuit so that a frequency of the clock signal supplied to the circuit is reduced when the calculated expected amount of current consumption exceeds a predetermined reference value.

20. The semiconductor apparatus according to claim 1, further comprising:

a first terminal that supplies the power supply voltage to the circuit; and

a second terminal that is supplied with the notification signal.

15. A semiconductor apparatus comprising:

a circuit including a predetermined function;

a power control circuit that controls power supplied to the circuit; and

a notification signal generating circuit that generates a notification signal for notifying a timing for the power control circuit to perform control.

16. The semiconductor apparatus according to claim 15, wherein a power supply voltage supplied to the circuit is adjusted according to the notification signal.

17. The semiconductor apparatus according to claim 15, wherein the notification signal generating circuit generates the notification signal when the power control circuit controls the circuit so that the power is supplied to the circuit.

18. The semiconductor apparatus according to claim 15, wherein

the power control circuit comprises a second state machine, and

the notification signal generating circuit generates the notification signal according to a state of the second state machine.

19. The semiconductor apparatus according to claim 18, wherein the notification signal generating circuit generates the notification signal in a period when the second state machine performs a process to supply the power to the circuit.

21. A system comprising:

a semiconductor apparatus comprising;

a circuit including a predetermined function;

a clock generating circuit that generates a clock signal supplied to the circuit;

a clock control circuit that controls the clock generating circuit; and

a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit; and

a power supply apparatus that supplies power to the semiconductor apparatus.

22. The system according to claim 21, wherein the power supply apparatus increases a voltage of the power supplied to the semiconductor apparatus in a period when a signal in an active state is supplied as the notification signal.