Switching System and Method

• US 20130009725A1
• Filed: 10/18/2010
• Published: 01/10/2013
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Ferfics Limited
• Original Assignee: Ferfics Limited
• Inventors: Heaney, Eugene, O'Sullivan, John, Kenney, Stephen
• Granted Patent: US 9,524,985 B2
• Time in Patent Office: Days
• US Class Current: 333/103
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) for switching at least one or more RF signals and said SOI comprises a bulk substrate region and a buried oxide region. At least one filter is adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system. There is also provided a coupling capacitor adapted to cooperate with the filter to improve linearity of the transistor switch elements.

Claims

1. A Radio Frequency (RF) system comprising:

a RF switch comprising a plurality of transistor switching elements implemented on Silicon on Insulator (SOI) substrate for switching at least one or more RF signals;

said SOI comprises a bulk substrate region and a buried oxide region;

characterised by;

at least one filter adapted to isolate the RF signal from the substrate and/or other high frequency signals or control signals present in the RF system.

2. The RF system of claim 1 wherein a coupling capacitor is adapted to cooperate with said at least one filter to improve linearity of the transistor switch elements.

3. The RF system as claimed in claim 1 comprising a trench implant layer adapted with means for capturing free carriers at the interface between the bulk substrate region and buried oxide region.

4. The RF system as claimed in claim 1 wherein the at least one filter is coupled to a gate bias line of at least one of said transistor switching elements.

5. The RF system as claimed in claim 1 wherein the at least one filter is coupled to a gate bias line and body bias line of at least one of said transistor switching elements.

6. The RF system as claimed in claim 1 wherein gate and body bias signals are connected to the at least one filter which is connected to a bias resistor and connected to the source or drain of the switch transistor through a capacitor.

7. The RF system as claimed in claim 1 wherein partial filtering occurs locally at the at least one transistor and further filtering occurs at the digital block and negative voltage generator circuit blocks.

8. The RF system as claimed in claim 1 wherein the width of the first and last transistor in the switch is reduced to fit the coupling capacitors into the same switch area without the coupling capacitors.

9. The RF system as claimed in claim 1 wherein the trench implant layer substantially surrounds at least one of the transistor switching elements.

10. The RF system as claimed in claim 1 wherein at least one transistor comprises a connected drain-source resistor, Rds, to improve the linearity performance of the RF system.

11. The RF system of claim 1 wherein the plurality of transistors are arranged in a stacked configuration.

12. The RF system of claim 1 comprising metal interconnects to connect the drain of a first transistor to the source of the next transistor arranged in series.

13. The RF system of claim 1 comprising metal interconnects to connect the drain of a first transistor to the source of the next transistor arranged in series wherein a trench layer is positioned underneath the metal contact layers and/or metal interconnects tracks in the RF system.

14. The RF system of claim 1 wherein said system comprises a digital control block and a negative voltage generator.

15. The RF system as claimed in claim 1 wherein said system comprises a digital control block and a negative voltage generator and the at least one filter comprises means to isolate the digital control block and the negative voltage generator from high power high frequency signals present in the RF system.

16. The RF system as claimed in claim 1 wherein said system comprises a digital control block and a negative voltage generator, the negative voltage generator comprises an oscillator circuit, a clock generator circuit and a charge pump.

17. The RF system as claimed in claim 1 wherein said system comprises a digital control block and a negative voltage generator, the digital logic block comprises means to control the on-off state of the transistor elements of the RF system.

18. A method of manufacturing an RF system comprising the steps of:

arranging a plurality of transistor switching elements implemented on Silicon on Insulator (SOI), said SOI comprises a bulk substrate region and a buried oxide region; and

positioning at least one filter adapted to isolate a RF signal from the substrate and/or other high frequency signals or control signals present in the RF system.

19. The method of claim 18 comprising the step of implanting a trench implant layer between said substrate and buried oxide region for capturing free carriers at the interface between the bulk substrate region and buried oxide region.

20. The method of claim 18 comprising the step of implanting a trench implant layer wherein the trench implant layer substantially surrounds at least one of the transistor switching elements.