PACKAGED DEVICE AND METHOD OF FABRICATING PACKAGED-DEVICE

• US 20130010447A1
• Filed: 09/14/2012
• Published: 01/10/2013
• Est. Priority Date: 09/18/2008
• Status: Active Grant

• Current Assignee: DRNC Holdings, Inc. (InterDigital, Inc.)
• Original Assignee: Fujitsu Limited
• Inventors: Inoue, Hiroaki, Katsuki, Takashi, Nakazawa, Fumihiko
• Granted Patent: US 9,372,202 B2
• Time in Patent Office: Days
• US Class Current: 361/803
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base

Abstract

A method includes forming grooves in first regions included in a first wafer to form wiring regions defined by the grooves; forming insulating portions in the grooves; joining a surface of the first wafer on which the wiring regions are formed to a first surface of a device wafer including device forming regions after forming the insulating portions; forming through holes in the wiring regions of the first wafer after joining the first wafer to the device wafer, the holes extending through the first wafer; filling the holes with a conductive material; joining a second wafer to a second surface of the device wafer opposite the first surface, the second wafer including second regions; exposing the wiring regions by thinning the first wafer after joining the first wafer to the device wafer; and cutting the device wafer, the first wafer, and the second wafer after thinning the first wafer.

Claims

1-9. -9. (canceled)

10. A packaged device comprising:

a device layer section in which a movable microdevice including a movable part and a terminal part is formed;

a first packaging member joined to the device layer section, and including a wiring region provided at a position corresponding to the terminal part and a conductive plug extending through the wiring region; and

a second packaging member joined to a side of the device layer section opposite the first packaging member.

11. The packaged device according to claim 10, further comprising:

an insulating film provided on a surface of the first packaging member, and including a first opening at a position corresponding to the wiring region; and

a first electrode pad electrically coupled to the wiring region at the first opening.

12. The packaged device according to claim 11, wherein the first electrode pad is provided in the first opening in an in-plane direction of the first packaging member.

13. The packaged device according to claim 11,

wherein the first packaging member includes a non-wiring region,

wherein the insulating film includes a second opening at a position corresponding to the non-wiring region, and

wherein a second electrode pad is provided, the second electrode pad electrically coupled to the non-wiring region at the second opening.

14. The packaged device according to claim 13, wherein the second electrode pad is provided in the second opening in an in-plane direction of the first packaging member.

15. The packaged device according to claim 10, wherein the first packaging member includes a recess facing the movable part of the movable microdevice.

16. The packaged device according to claim 10, wherein the second packaging member includes a recess facing the movable part of the movable microdevice.