SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

• US 20130010556A1
• Filed: 09/15/2012
• Published: 01/10/2013
• Est. Priority Date: 01/20/2009
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: KOSHIZUKA, Atsuo
• Granted Patent: US 8,811,054 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,

Claims

1. A system, comprising:

a controller comprising a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data; and

a semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,

one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,

2. The system as claimed in claim 1, the device further comprising:

a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.

3. The system as claimed in claim 1,

wherein the length of the preamble is a first length when a first information indicates a first value.

4. The system as claimed in claim 3,

wherein the length of the preamble is a second length different from the first length when the information indicates a second value different from the first value.

5. The system as claimed in claim 1,

wherein the preamble comprises a read preamble.

6. The system as claimed in claim 1,

wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.

7. The system as claimed in claim 1, the controller further comprising:

a preamble length determination unit configured to determine the length of the preamble.

8. The system as claimed in claim 7,

wherein the preamble length determination unit determines the length of the preamble based on a variation of a delay time of the strobe signal.

9. The system as claimed in claim 7,

wherein the preamble length determination unit determines the length of the preamble for each fixed time interval.

10. A system, comprising:

a semiconductor memory device and a controller,

the semiconductor memory device comprising;

a first external terminal provided to receive a clock signal;

a second external terminal provided to receive a read command;

a third external terminal configured to output a data strobe signal in response to the read command, the data strobe signal including a read preamble and a toggle transition following to the preamble;

a fourth external terminal provided to output a read data in synchronization with the toggle transition of the data strobe signal; and

a control circuit configured to control a length of the read preamble of the data strobe signal based on a preamble length information,

the controller comprising;

a fifth external terminal provided to output the clock signal;

a sixth external terminal provided to output the read command;

a seventh external terminal provided to receive the read data;

an eighth external terminal provided to receive the data strobe signal related to the read data; and

a ninth external terminal provided to output the preamble length information.

11. The system as claimed in claim 10,

wherein the length of the read preamble is set to a first length when the information indicates a first value.

12. The system as claimed in claim 11,

wherein the length of the read preamble is set to a second length different from the first length when the information indicates a second value different from the first value.

13. The system as claimed in claim 10, the controller further comprising:

a preamble length determination unit configured to determine the length of the read preamble.

14. The system as claimed in claim 13,

wherein the preamble length determination unit determines the length of the read preamble based on a variation of a delay time of the strobe signal.

15. The system as claimed in claim 13,

wherein the preamble length determination unit determines the length of the read preamble at a system start-up time.

16. The system as claimed in claim 13,

wherein the preamble length determination unit determines the length of the read preamble for each fixed time interval.

17. A system, comprising:

a semiconductor memory device and a controller;

the semiconductor memory device comprising;

a first external terminal provided to receive a clock signal;

a second external terminal provided to transfer a data with the controller in synchronization with the clock signal;

a third external terminal provided to receive a command for communicating the data;

a control circuit configured to produce a data strobe signal, which includes a preamble and a toggle transition following to the preamble, so that the transferring the data is conducted by the toggle transition of the data strobe signal; and

a fourth external terminal provided to be supplied an information specifying a length of the preamble of the strobe signal,

the controller, comprising;

a fifth external terminal provided to output the clock signal;

a sixth external terminal provided to communicate the data;

a seventh external terminal configured to output the command; and

an eighth external terminal configured to output the information.

18. The system as claimed in claim 17,

wherein the length of the preamble is set to a first length when the information indicates a first value, and the length of the preamble is set to a second length different from the first length when the information indicates a second value different from the first value.

19. The system as claimed in claim 17, the controller further comprising:

a preamble length determination unit configured to determine the length of the preamble.

20. The system as claimed in claim 17,

wherein the data strobe signal is transferred from the semiconductor memory device to the controller when performing a read operation.