TEST SIGNAL GENERATION AND APPLICATION IN RECEIVERS

• US 20130010851A1
• Filed: 07/08/2011
• Published: 01/10/2013
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Jaeger, Herbert, Wagner, Christoph
• Granted Patent: US 9,059,879 B2
• Time in Patent Office: Days
• US Class Current: 375/224
• CPC Class Codes: H04B 1/302 for single sideband receivers demodulator circuits H03D1/24
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 17/29 Performance testing
• CPC Class Codes: H04L 1/244 test sequence generators
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

One embodiment of the present invention relates to a test signal generator configured to generate a single sideband (SSB) test signal that is used for testing components of one or more receiver chains to identify errors in the receiver chains. In one embodiment, the circuit comprises a SSB signal generator configured to generate an IQ baseband signal comprising a sequence of constellation points corresponding to the SSB test signal. The constellation points are modulated onto a high frequency local oscillator signal to generate the SSB test signal, which is inserted into a reception path of a receiver at a test signal injection point. The reception path comprises a mixer configured to mix the SSB test signal with the local oscillator signal to generate a down-converted, intermediate frequency output signal. The output signal may be analyzed to determine errors in the reception path.

Claims

1. A receiver circuit, comprising:

a test signal generation component configured to generate a single side band (SSB) test signal independent from a signal received by a reception path of the receiver circuit;

a test signal injection point configured to provide the SSB test signal to the reception path of the receiver circuit; and

a mixer located within the reception path at a location downstream of the test signal injection point, the mixer configured to mix the SSB test signal with a local oscillator signal to generate a down-converted output signal indicative of an error in the reception path.

2. The receiver circuit of claim 1, wherein the test signal generation component, comprises:

a single sideband (SSB) signal generator configured to generate an IQ baseband signal comprising a sequence of constellation points, wherein the IQ baseband signal has an in-phase signal component and a quadrature phase signal component; and

an IQ modulator configured to receive the IQ baseband signal and to generate the SSB test signal by modulating the IQ baseband signal onto the local oscillator signal.

3. The receiver circuit of claim 2, further comprising:

a first multiplier located downstream of the SSB signal generator and configured to amplify a magnitude of the in-phase signal component based upon an amplitude setting word; and

a second multiplier located downstream of the SSB signal generator and configured to amplify a magnitude of the quadrature phase signal component based upon the amplitude setting word.

4. The receiver circuit of claim 2, further comprising:

a first adder located downstream of the SSB signal generator and configured to add or subtract an offset value to the in-phase signal component; and

a second adder located downstream of the SSB signal generator and configured to add or subtract an offset value to the quadrature phase signal component.

5. The receiver circuit of claim 2, wherein the SSB signal generator is configured to receive a low frequency digital clock signal at a digital clock input and to generate the IQ baseband signal therefrom.

6. The receiver circuit of claim 5, wherein the SSB signal generator comprises one or more frequency dividers configured to generate the sequence of constellation points based upon the low frequency digital clock signal.

7. The receiver circuit of claim 6, wherein the SSB signal generator comprises:

a divide-by-two frequency divider configured to divide the low frequency digital clock signal by two to generate a divided-by-two clock signal; and

a Johnson counter configured to receive the divided-by-two clock signal and to generate the in-phase and the quadrature phase signal components therefrom.

8. The receiver circuit of claim 2, wherein the sequence of constellation points comprise a first sequence that corresponds to a SSB test signal having a positive frequency single sideband or having a second sequence that corresponds to a SSB test signal having a negative frequency single sideband.

9. The receiver circuit of claim 1, further comprising:

a plurality of additional receiver paths, wherein respective additional receiver paths comprise an additional test signal injection point and an additional mixer located downstream of the additional test signal injection point; and

a distribution network comprising a symmetric power splitter configured to supply the SSB test signal to the test signal injection points of respective additional receiver paths;

wherein the additional mixers are configured to mix the SSB test signal with a local oscillator signal to generate a down-converted output signals indicative of errors in the additional reception paths.

10. The receiver circuit of claim 9, wherein the symmetric power splitter is configured to provide the SSB test signal having a substantially equal phase to all reception paths so that a comparison between the down-converted output signals of each reception path can be made, to generate information of phase drift between reception paths.

11. The receiver circuit of claim 9, wherein the receiver circuit is comprised within a digital beamforming radar.

12. The receiver circuit of claim 1, wherein the test signal generation component, the test signal injection point, and the mixer are comprised within a single integrated chip.

13. A circuit, comprising:

a single sideband (SSB) signal generator having a digital clock input configured to receive a low frequency digital clock signal, wherein the SSB signal generator is configured to generate in-phase and quadrature phase signal components of a baseband IQ signal, comprising a sequence of constellation points, from the low frequency digital clock signal;

an IQ modulator configured to modulate the baseband IQ signal onto a local oscillator signal to generate a single sideband (SSB) test signal;

one or more reception paths coupled to an antenna and respectively configured to receive one or more RF signals;

one or more couplers in direct communication with the one or more reception paths and configured to provide the SSB test signal to the one or more reception paths; and

one or more mixers respectively disposed within the one or more reception paths at a location downstream of the one or more couplers, the one or more mixers configured to mix the SSB test signal with the local oscillator signal to generate one or more output signals indicative of an error in the reception paths.

14. The circuit of claim 13, wherein the sequence of constellation points traverse 360°

in an I/O plane in a clockwise or a counter clock-wise direction.

15. The circuit of claim 13, wherein the SSB test signal is generated independent from the one or more RF signals received by the one or more reception paths.

16. The circuit of claim 13, further comprising:

a first multiplier located downstream of the SSB signal generator and configured to amplify a magnitude of the in-phase signal component based upon an amplitude setting word; and

a second multiplier located downstream of the SSB signal generator and configured to amplify a magnitude of the quadrature phase signal component based upon the amplitude setting word, wherein the first and second multipliers are configured to effectively turn off the SSB signal generator by setting the amplitude of the I and Q signals to substantially zero.

17. A method for testing one or more reception paths of a receiver circuit, comprising:

generating a single sideband (SSB) test signal independent from an RF signal received by the receiver circuit;

injecting the SSB test signal into a reception path configured to receive the RF signal; and

down-converting the SSB test signal using a local oscillator signal to generate an output signal indicative of an error in the reception path.

18. The method of claim 17, wherein generating a SSB test signal, comprises:

generating an IQ baseband signal comprising a sequence of constellation points by division of a digital clock signal by one or more frequency dividers; and

modulating the IQ baseband signal onto the local oscillator signal to generate the SSB test signal.

19. The method of claim 18, further comprising:

adjusting an amplitude of the IQ baseband signal prior to modulation onto the local oscillator signal.

20. The method of claim 18, wherein the sequence of constellation points spans 360°

in an I/O plane.