Conductivity Based on Selective Etch for GaN Devices and Applications Thereof

• US 20130011656A1
• Filed: 07/26/2012
• Published: 01/10/2013
• Est. Priority Date: 01/27/2010
• Status: Active Grant

• Current Assignee: Yale University
• Original Assignee: Yale University
• Inventors: Han, Jung, Zhang, Yu, Sun, Qian
• Granted Patent: US 9,206,524 B2
• Time in Patent Office: Days
• US Class Current: 428/312.8
• CPC Class Codes: C25B 1/04 by electrolysis of water
• CPC Class Codes: C25B 1/55 Photoelectrolysis
• CPC Class Codes: C25F 3/12 of semiconducting materials
• CPC Class Codes: C30B 23/025 characterised by the substrate
• CPC Class Codes: C30B 25/186 being specially pre-treated by, e.g. chemical or physical means
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: C30B 33/10 in solutions or melts
• CPC Class Codes: G02B 1/02 made of crystals, e.g. rock-salt, semi-conductors G02B1/08 takes precedence
• CPC Class Codes: G02B 1/118 having sub-optical wavelength surface structures designed to provide an enhanced transmittance, e.g. moth-eye structures
• CPC Class Codes: G02B 2207/107 Porous materials, e.g. for reducing the refractive index
• CPC Class Codes: G02B 5/1861 Reflection gratings characterised by their structure, e.g. step profile, contours of substrate or grooves, pitch variations, materials G02B5/1809, G02B5/1828, G02B5/1833, G02B5/1838 and G02B5/1847 take precedence
• CPC Class Codes: G02B 6/29356 Interference cavity within a single light guide, e.g. between two fibre gratings G02B6/29347 - G02B6/2935 take precedence; evanescent coupling to a resonator cavity G02B6/29335
• CPC Class Codes: G02B 6/29358 Multiple beam interferometer external to a light guide, e.g. Fabry-Pérot, etalon, VIPA plate, OTDL plate, continuous interferometer, parallel plate resonator G02B6/29347, G02B6/29349, G02B6/2935, G02B6/29361 take precedence; resonator evanescently coupled to light guide G02B6/29335
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/02005 Preparing bulk and homogeneous wafers
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 : Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02658 : Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/306 : Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30612 : Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/30625 : With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/30635 : of AIIIBV compounds
• CPC Class Codes: H01L 21/326 : Application of electric currents or fields, e.g. for electroforming H01L21/20 - H01L21/288 and H01L21/302 - H01L21/324 take precedence
• CPC Class Codes: H01L 21/7813 : leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 33/0025 : comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/0062 : for devices with an active region comprising only III-V compounds
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0075 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/16 : with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: Y02E 60/36 : Hydrogen production from non-carbon containing sources, e.g. by water electrolysis
• CPC Class Codes: Y10T 428/24997 : Of metal-containing material

Abstract

This invention relates to methods of generating NP gallium nitride (GaN) across large areas (>1 cm²) with controlled pore diameters, pore density, and porosity. Also disclosed are methods of generating novel optoelectronic devices based on porous GaN. Additionally a layer transfer scheme to separate and create free-standing crystalline GaN thin layers is disclosed that enables a new device manufacturing paradigm involving substrate recycling. Other disclosed embodiments of this invention relate to fabrication of GaN based nanocrystals and the use of NP GaN electrodes for electrolysis, water splitting, or photosynthetic process applications.

Claims

1. A method for generating porous GaN, comprising:

(a) exposing GaN to an electrolyte;

(b) coupling the GaN to one terminal of a power supply and an electrode immersed in the electrolyte to another terminal of the power supply to thereby form a circuit; and

(c) energizing the circuit to increase the porosity of at least a portion of the GaN.

2. The method of claim 1, further comprising applying a voltage in the range between 5V and 60V, wherein the GaN is coupled to the positive terminal of the power supply.

3. The method of claim 1, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

4. The method of claim 1, further comprising doping at least a portion of the GaN in the range from 10¹⁷ to 10¹⁹ cm⁻

3, and providing the electrolyte as KOH or HCl.

5. The method of claim 1, further comprising doping at least a portion of the GaN in the range from 10¹⁷ to 10¹⁹ cm⁻

3, and providing the electrolyte as oxalic acid.

6. The method of claim 5, further comprising applying a voltage in the range between 5V and 60V, wherein the doped GaN is coupled to the positive terminal of the power supply.

7. The method of claim 5, wherein the energizing further comprises controlling an applied voltage or current to adjust the GaN porosity.

8. The method of claim 5, further comprising forming a doping profile in the GaN prior to the energizing to generate a corresponding porosity profile.

9. The method of claim 8, wherein the energizing further comprises controlling an applied voltage between a low and high value in the range between 0V and 60V as a function of time to generate the porosity profile.

10. The method of claim 1, further comprising:

(a) providing the electrolyte as oxalic acid;

(b) coupling the GaN to the positive terminal of the power supply; and

(c) applying a voltage in the range between 0V and 60V.

11. The method of claim 10, further comprising switching the voltage between a low and high value in the range between 0V and 60V as a function of time to generate a porosity profile.

12. The method of claim 10, further comprising forming an n-type multi-layer doping profile in the GaN, wherein the energizing generates a porosity profile with a refractive index periodicity of a quarter-wavelength distributed Bragg reflector (DBR).

13. The method of claim 11, further comprising forming a uniform n-type doping in the GaN, wherein the energizing causes the porosity profile to have a refractive index periodicity of a quarter-wavelength distributed Bragg reflector (DBR).

14. The method of claim 12, further comprising disposing an undoped or uniformly doped GaN structure between two such DBRs to form a Fabre-Perot optical filter.

15. The method of claim 13, further comprising disposing an undoped or uniformly doped GaN structure between two such DBRs to form a Fabre-Perot optical filter.

16. The method of claim 11, further comprising doping to form a doped surface layer in the GaN, wherein the energizing transforms the doped surface layer into a NP surface layer to enhance light extraction.

17. The method of claim 11, further comprising:

(a) forming a doping profile in the GaN; and

(b) etching the layer to form a NP template.

18. The method of claim 17, further comprising disposing on said template:

(a) n-type GaN,

(b) p-type GaN, and

(c) InGaN/GaN active layers between (a) and (b) to form a light emitting diode (LED).

19. The method of claim 8, further comprising:

(a) forming a doping profile in the GaN material; and

(b) etching the GaN material to form a first, low-porosity, continuous crystalline layer, and a second, high porosity layer underneath the first layer, wherein the second layer is mechanically weakened to facilitate the separation of the first low-porosity, continuous crystalline layer from the substrate.

20. The method of claim 9, further comprising:

(a) forming a doping profile in the GaN material; and

(b) etching the GaN material to form a first, low-porosity, continuous crystalline layer, and a second, high porosity layer underneath the first layer, wherein the second layer is mechanically weakened to facilitate the separation of the first low-porosity, continuous crystalline layer from the substrate.

21. The method of claim 11, further comprising:

(a) forming a doping profile in the GaN material; and

(b) etching the GaN material to form a first, low-porosity, continuous crystalline layer, and a second, high porosity layer underneath the first layer, wherein the second layer is mechanically weakened to facilitate the separation of the first low-porosity, continuous crystalline layer from the substrate.

22. The method of claim 21, wherein the forming further comprises doping the GaN uniformly at a concentration value ranging from 10¹⁸ to 10¹⁹ cm⁻

3, and the etching comprises

(i) applying a first voltage V₁ for a first time duration T₁; and

(ii) applying a second voltage V₂ for a second time duration T₂.

23. The method of claim 22, wherein the concentration value is 5×

10¹⁸ cm<sup>−

3</sup>, V₁ is 10V for the first time duration T₁ of 5 minutes, and V₂ is 15V for the second time duration V₂ of 1 minute.

24. The method of claim 19, further comprising:

(a) doping the GaN to form a first layer with a first doping concentration N₁ and a second layer of doping concentration N₂; and

(b) applying the voltage at a fixed value for a fixed period of time.

25. The method of claim 24, further comprising:

(a) doping the GaN with concentrations N₁=3×

10¹⁸ cm<sup>−

3</sup>, and N2=1×

10¹⁹ cm<sup>−

3</sup>; and

(b) applying the voltage at 12V for 5 minutes.

26. The method of claim 19, further continuing the etching process until the low-porosity continuous crystalline layer has completely separated from the substrate in electrolyte.

27. The method of claim 20, further continuing the etching process until the low-porosity continuous crystalline layer has completely separated from the substrate in electrolyte.

28. The method of claim 21, further continuing the etching process until the low-porosity continuous crystalline layer has completely separated from the substrate in electrolyte.

29. The method of claim 19, further comprising

(a) stopping the etching process before the low-porosity continuous crystalline layer has separated from the substrate in electrolyte;

(b) wafer bonding the low-porosity continuous crystalline layer to a target wafer or a polymer stamp; and

(c) mechanically detaching the bonded low-porosity continuous crystalline layer from the substrate.

30. The method of claim 19, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

31. The method of claim 8, further comprising:

(a) growing a device or epitaxial structure on said porous structure using epitaxial growth techniques;

(b) forming a buried voided layer underneath the device or epitaxial structure in (a) having weakened mechanical strength, through concurrent annealing and transformation during step (a)

(c) wafer bonding a carrier wafer to the surface of the device structure; and

(d) cleaving, at the buried voided layer, the device structure and the carrier wafer from substrate.

32. The method of claim 31, further comprising:

polishing a remaining portion of GaN on the substrate; and

repeating (a) through (d).

33. The method of claim 31, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

34. The method of claim 31, further comprising growing the device structure using an epitaxial method that is one of MOCVD, HVPE or MBE.

35. The method of claim 20, further comprising

(a) stopping the etching process before the low-porosity continuous crystalline layer has separated from the substrate in electrolyte;

(b) wafer bonding the low-porosity continuous crystalline layer to a target wafer or a polymer stamp; and

(c) mechanically detaching the bonded low-porosity continuous crystalline layer from the substrate.

36. The method of claim 20, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

37. The method of claim 9, further comprising:

(a) growing a device or epitaxial structure on said porous structure using epitaxial growth techniques;

(b) forming a buried voided layer underneath the said device or epitaxial structure in (a) having weakened mechanical strength, through concurrent annealing and transformation during step (a);

(c) wafer bonding a carrier wafer to the surface of the device structure; and

(d) cleaving, at the buried voided layer, the device structure and the carrier wafer from substrate.

38. The method of claim 37, further comprising:

polishing a remaining portion of GaN on the substrate; and

repeating (a) through (d).

39. The method of claim 37, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

40. The method of claim 37, further comprising growing the device structure using an epitaxial method that is one of MOCVD, HVPE or MBE.

41. The method of claim 21, further comprising

(a) stopping the etching process before the low-porosity continuous crystalline layer has separated from the substrate in electrolyte;

(b) wafer bonding the low-porosity continuous crystalline layer to a target wafer or a polymer stamp; and

(c) mechanically detaching the bonded low-porosity continuous crystalline layer from the substrate.

42. The method of claim 21;

further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

43. The method of claim 1 further comprising:

(a) growing a device or epitaxial structure on said porous structure using epitaxial growth techniques;

(b) forming a buried voided layer underneath the said device or epitaxial structure in (a) having weakened mechanical strength, through concurrent annealing and transformation during step (a);

(c) wafer bonding a carrier wafer to the surface of the device structure; and

(d) cleaving, at the buried voided layer, the device structure and the carrier wafer from substrate.

44. The method of claim 43, further comprising:

polishing a remaining portion of GaN on the substrate; and

repeating (a) through (d).

45. The method of claim 43, further comprising disposing the GaN on a substrate comprising sapphire, silicon, silicon carbide, or bulk GaN.

46. The method of claim 43, further comprising growing the device structure using an epitaxial method that is one of MOCVD, HVPE or MBE.

51. A quarter-wavelength distributed Bragg reflector (DBR) fabricated according to the method of claim 12.

52. A Fabry-Perot optical filter fabricated according to the method of claim 14.

53. A NP surface layer fabricated according to the method of claim 16.

54. A NP template fabricated according to the method of claim 17.

47. A method of manufacturing nanocrystals, comprising:

(a) providing a material comprising at least one of GaN or InGaN with a thin n-type doped surface layer;

(b) exposing the material to an electrolyte;

(c) coupling the material to one terminal of a power supply and an electrode immersed in the electrolyte to another terminal of the power supply to thereby form a circuit;

(d) energizing the circuit to drive a current through the circuit, wherein the current acts to create a thin porous layer at a surface of the material; and

,

(e) subjecting the porous layer to a mechanical disturbance to break the porous layer into a nanocrystals.

48. The method of claim 47 further comprising using a sonicator to provide the mechanical disturbance in the form of sound waves.

55. One or more nanocrystals fabricated according to claim 47.

49. A method of manufacturing an electrode, comprising:

(a) providing a material comprising at least one of GaN or InGaN with a thin n-type doped surface layer;

(b) exposing the material to an electrolyte;

(c) coupling the material to one terminal of a power supply and an electrode immersed in the electrolyte to another terminal of the power supply to thereby form a circuit; and

,

(d) energizing the circuit to drive a current through the material, wherein the current acts to create a thin porous layer on the surface to produce a structure suitable for use as an electrode for electrolysis, water splitting, or photosynthetic process applications.

50. A method of efficient solar water splitting, comprising:

(a) providing an anode of porous GaN or InGaN electrode manufactured according to the method of claim 49;

(b) providing a metal cathode electrode;

(c) exposing the anode and the cathode to an electrolyte;

(d) electrically connecting the anode and the cathode so as to form an electrical circuit; and

,

(e) exposing the anode to solar radiation so as to induce a photo-current in the circuit and thereby drive a photo-chemical water splitting chemical reaction.

56. A porous electrode fabricated according to claim 49.