In-Situ Doping of Arsenic for Source and Drain Epitaxy

• US 20130011983A1
• Filed: 07/07/2011
• Published: 01/10/2013
• Est. Priority Date: 07/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yao-Tsung, Ko, Chih-Hsin, Wann, Clement Hsingjen, Tsai, Ji-Yin
• Granted Patent: US 8,962,400 B2
• Time in Patent Office: Days
• US Class Current: 438/285
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.

Claims

1. A method comprising:

forming a gate stack over a semiconductor region;

recessing the semiconductor region to form a recess adjacent the gate stack; and

epitaxially growing a silicon-containing semiconductor region in the recess to form a source/drain stressor, wherein arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.

2. The method of claim 1, wherein in the step of epitaxially growing the silicon-containing semiconductor region, a precursor selected from the group consisting essentially of AsH₃, trimethyl arsenic (TMAs), tertiarybutylarsine (TBAs), and combination thereof is used.

3. The method of claim 1, wherein the silicon-containing semiconductor region comprises a silicon germanium stressor.

4. The method of claim 1, wherein the silicon-containing semiconductor region comprises a silicon stressor that is substantially free from germanium.

5. The method of claim 1 further comprising a step of forming the semiconductor region, wherein the step of forming the semiconductor region comprises:

forming isolation regions in a semiconductor substrate;

etching a portion of the semiconductor substrate between opposite sidewalls of the isolation regions to form a recess;

epitaxially growing a first silicon germanium layer in the recess; and

epitaxially growing a second silicon germanium layer in the recess and over the first silicon germanium layer, wherein the second silicon germanium layer has a lower germanium concentration than the first silicon germanium layer.

6. The method of claim 5 further comprising recessing the isolation regions, so that a portion of the second silicon germanium layer forms a semiconductor fin that is above top surfaces of remaining portions of the isolation regions, wherein the gate stack comprises a first portion directly over the semiconductor fin, and a second portion on a sidewall of the semiconductor fin.

7. The method of claim 1 further comprising a step of forming the semiconductor region, wherein the step of forming the semiconductor region comprises:

forming isolation regions in a semiconductor substrate; and

etching a portion of the semiconductor substrate between opposite sidewalls of the isolation regions to form a recess;

epitaxially growing a silicon germanium layer in the recess; and

epitaxially growing a group-III and group-V containing (III-V) compound semiconductor layer over the silicon germanium layer.

8. A method comprising:

epitaxially growing a silicon germanium layer over a portion of a silicon substrate;

epitaxially growing a semiconductor layer over the silicon germanium layer, wherein the semiconductor layer has a first lattice constant smaller than a second lattice constant of the silicon germanium layer;

forming a gate stack over the semiconductor layer, wherein a portion of the semiconductor layer forms a channel region of an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET);

recessing the semiconductor layer to form recesses on opposite sides of the gate stack; and

epitaxially growing semiconductor stressors in the recesses, wherein the semiconductor stressors have a third lattice constant smaller than the first lattice constant, and wherein during the step of epitaxially growing the semiconductor stressors, arsenic is in-situ doped.

9. The method of claim 8, wherein during the step of epitaxially growing the semiconductor stressors, a precursor selected from the group consisting essentially of AsH₃, trimethyl arsenic (TMAs), tertiarybutylarsine (TBAs), and combination thereof is used.

10. The method of claim 8 further comprising:

forming isolation regions in the silicon substrate; and

etching a portion of the silicon substrate between opposite sidewalls of the isolation regions to form a recess, wherein the silicon germanium layer and the semiconductor layer are epitaxially grown in the recess.

11. The method of claim 10 further comprising recessing the isolation regions, so that the semiconductor layer forms a semiconductor fin, wherein the gate stack comprises a first portion directly over the semiconductor fin, and a second portion on a sidewall of the semiconductor fin.

12. A method comprising:

forming isolation regions in a silicon substrate;

forming a gate stack on a top surface of the silicon substrate;

recessing portions of the silicon substrate on opposite sides of the gate stack to form recesses; and

epitaxially growing silicon-containing semiconductor regions in the recesses to form source/drain regions of a planar transistor, wherein the step of epitaxially growing is performed simultaneously with an in-situ doping of arsenic.

13. The method of claim 12, wherein the step of epitaxially growing the silicon-containing semiconductor regions comprises growing silicon germanium regions.

14. The method of claim 12, wherein the step of epitaxially growing the silicon-containing semiconductor regions comprises growing silicon regions that are substantially free from germanium.

15. The method of claim 12, wherein during the step of epitaxially growing the silicon-containing semiconductor regions, AsH₃ is used as a process gas.