METHOD FOR PRODUCING A WAFER PROVIDED WITH CHIPS

• US 20130011997A1
• Filed: 03/31/2010
• Published: 01/10/2013
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: EV Group E Thallner GmbH (Thallner Privatstiftung)
• Original Assignee: EV Group E Thallner GmbH (Thallner Privatstiftung)
• Inventors: Wimplinger, Markus, Wiesbauer, Harald, Burggraf, Jrgen
• Granted Patent: US 9,224,630 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2221/68386 Separation by peeling
• CPC Class Codes: H01L 2221/6839 using peeling wedge or knife or bar
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A method for producing a product wafer having chips thereon, comprising the steps of:

• processing the first side of the product wafer
• bonding the product wafer with its first side onto a first rigid carrier wafer with a first intermediate layer consisting of one first adhesion layer applied at least on the edge side,
• processing a second side of the product wafer,
• bonding of the product wafer with its second side on a second rigid carrier wafer with a second intermediate layer consisting of one second adhesion layer applied at least on the edge side, characterized in that the first intermediate layer and the second intermediate layer are made different such that the first carrier wafer can be separated selectively before the second carrier wafer.

Claims

1. Method for producing a product wafer which is provided with chips, which proceeds as follows:

bonding of a first side of the product wafer on a first rigid carrier wafer with a first intermediate layer consisting of one first adhesion layer applied at least on the edge side,

bonding of a second side of the product wafer opposite to the first side on a second rigid carrier wafer with a second intermediate layer consisting of one second adhesion layer applied at least on the edge side, wherein the first intermediate layer and the second intermediate layer are made different such that both rigid carrier wafers bonded to the product wafer can be separated selectively from the product wafer.

2. Method as claimed in claim 1, wherein the bonding force of the first adhesion layer is smaller than the bonding force of the second adhesion layer.

3. Method as claimed in claim 1, wherein the first adhesion layer has smaller dimensions than the second adhesion layer, especially a smaller contact area of the first adhesion layer with the first carrier wafer and the product wafer and/or a thinner layer thickness.

4. Method as claimed in claim 1, wherein the first adhesion layer has chemical properties different from the second adhesion layer such that the first adhesion layer is at least partially dissolved by a first solvent, while the second adhesion layer is at least largely inert with reference to the first solvent.

5. Method as claimed in claim 1, wherein the first intermediate layer has different thermal properties from the second intermediate layer such that the first intermediate layer with rising temperature is at least partially dissolved so that the separation of the first carrier wafer can be effected before separation of the second carrier wafer.

6. Method as claimed in claim 1, wherein the separation of the first carrier wafer from the product wafer takes place selectively as a result of different optical properties of the first intermediate layer and the second intermediate layer, especially with reference to the action of defined light source [sic] lengths and/or defined light intensities of a light source which acts preferably selectively on the first adhesion layer and/or the second adhesion layer.

7. Method as claimed in claim 1, wherein the separation of the first carrier wafer from the product wafer takes place selectively as a result of different mechanical properties of the first intermediate layer and the second intermediate layer, especially with reference to the shear strength, preferably the shear strength as a function of the temperature.

8. Method as claimed in claim 1, wherein the first and/or the second adhesion layer are made annular, especially in the region of the periphery of the product wafer.

9. Method as claimed in claim 1, wherein between the first carrier wafer and the first intermediate layer a first partial coating applied especially on the first carrier wafer is applied for reducing the bonding force/adhesion force in the region of the first partial coating and/or between the second carrier wafer and the second intermediate layer a second partial coating applied especially on the second carrier wafer is applied for reducing the bonding force/adhesion force in the region of the second partial coating.