HOST CONTROLLER

• US 20130013822A1
• Filed: 09/14/2012
• Published: 01/10/2013
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Feeley, Peter, Leibowitz, Robert N., Radke, William H., Galbo, Neal A., Tsai, Victor Y.
• Granted Patent: US 8,578,070 B2
• Time in Patent Office: Days
• US Class Current: 710/24
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Claims

1. A method for controlling a memory device, comprising:

storing device class dependent information and a command in one or more of host system memory and host controller memory, wherein the device class dependent information and the command are associated with a memory device external to a host system that includes one or more of host system memory and host controller memory;

setting a pointer to the command in a register in a host controller;

directing access of the memory device to the command in the one or more of host system memory and host controller memory using the pointer via the host controller; and

executing the command with the memory device.

2. The method of claim 1, wherein directing access to the host system memory includes managing direct memory access (DMA) of data and providing flow control of data between a host and the memory device with the host controller.

3. The method of claim 2, wherein directing access to the host system memory includes managing DMA of data and providing flow control without host processor intervention.

4. The method of claim 1, wherein the method includes storing device class independent information in one or more registers in the host controller.

5. The method of claim 4, wherein storing device class independent information includes storing one or more types of information selected from the group including:

device control and interrupt information;

device enable/disable information;

device power state control/status information;

one or more pointers to device-class dependent information in the host system memory;

one or more pointers to commands in the host system memory;

a particular device class associated with a particular transaction layer register entry; and

a reset command.

6. The method of claim 1, wherein the command is written with small computer system interface (SCSI) protocol.

7. The method of claim 6, wherein the command is modified with the device class dependent information and the device class independent information.

8. The method of claim 1, wherein directing access to the one or more of host system memory and host controller memory with the memory device via the host controller includes providing access to a read command and a write command and executing the read command and write command with the memory device.

9. A method for operating a memory device, comprising:

storing device class dependent information in a memory array;

building a read command in the memory array with a host system processor based on the device class dependent information;

locating the read command in the memory array using a pointer stored in a register in a host controller, wherein the pointer indicates the location of the read command in the memory array;

sending the read command from the memory array to the memory device via a host system controller, wherein the memory device is external to a host system that includes the memory array; and

executing the read command with the memory device by initiating a direct memory access (DMA) write from the memory device to the memory array with the memory device.

10. The method of claim 9, wherein the method includes:

allocating data space in the memory array for the read command data with the host system processor; and

setting an identifier associated with the read command with the host system processor, wherein the identifier indicates a location of the data space in the memory array for the read command data.

11. The method of claim 10, wherein the identifier is a segment identifier (SID) and wherein the SID locates a base address in a SID table in the one or more of host system memory and host controller memory for the location of read command data.

12. The method of claim 11, wherein the SID identifies a range of addresses in the one or more of host system memory and host controller memory indicating valid locations for the read command data.

13. The method of claim 10, wherein the method includes initiating a memory write to the data space allocated in the memory array at the location indicated by the identifier associated with the read command by the memory device.

14. The method of claim 9, wherein the memory array is a memory array type selected from the group including host system memory and host controller memory.

15. The method of claim 9, wherein the method includes updating the read command with a completion status in the memory array with the memory device.

16. A memory system, comprising:

a host system that includes a host controller having host controller memory and a host processor coupled to the host controller; and

one or more memory devices each coupled to at least one other of the one or more memory devices and to the host system via a bus, wherein the one or more memory devices are external to the host system,

wherein the host controller locates commands in host system memory and/or host controller memory using a pointer in a register in the host controller to the commands based on device class dependent information stored in the host system memory and/or host controller memory, transmits the commands to the one or more memory devices, and the one or more memory devices execute the commands with a memory device controller on the one or more memory devices to read data from and/or write data to the one or more memory devices.

17. The system of claim 16, wherein the host controller has a hardware port and a peripheral device is coupled to the hardware port.

18. The system of claim 17, wherein the host controller transmits commands built by the host processor in the host system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to the peripheral device.

19. The system of claim 16, wherein the host controller transmits commands built by the host processor in the host system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to system memory.

20. The system of claim 16, wherein the host controller transmits commands built by the host processor in the host system memory and/or the host controller memory to the number of memory devices to read data from and/or write data to host controller memory.