Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating

• US 20130015517A1
• Filed: 02/07/2011
• Published: 01/17/2013
• Est. Priority Date: 02/07/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Granted Patent: US 9,153,309 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Claims

1-175. -175. (canceled)

176. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a substrate terminal connected to said substrate;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

one of a bit line terminal and a source line terminal connected to said first region;

a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;

the other of said bit line terminal and said source line terminal connected to said second region;

a trapping layer positioned in between the first and second locations and above a surface of the substrate;

the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, wherein said first and second storage locations are each configured to receive transfer of data stored by the volatile memory; and

a control gate positioned above the trapping layer.

177. The semiconductor memory cell of claim 176, wherein the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type;

and

a buried well terminal connected to said buried layer.

178. The semiconductor memory cell of claim 177, wherein said floating body is completely bounded by said top surface, said first and second regions and said buried layer.

180. The semiconductor memory cell of claim 176, further comprising insulating layers bounding the side surfaces of the substrate.

183. The semiconductor memory cell of claim 176, wherein said floating body is configured so that more than one bit of data can be stored therein.

179. (canceled)

181-182. -182. (canceled)

184-192. -192. (canceled)

193. A semiconductor memory cell comprising:

a floating body region for storing data as volatile memory; and

a trapping layer for storing data as non-volatile memory;

wherein the data stored as volatile memory and the data stored as non-volatile memory are independent of one another, as said floating body region can be operated independently of said trapping layer and said trapping layer can be operated independently of said floating body region.

194. The cell of claim 193, wherein the floating body region has a first conductivity type and is bounded by a buried layer have a second conductivity type different from said first conductivity type.

196. The cell of claim 193, wherein the floating body region is bounded by a buried insulator.

197. The cell of claim 193, wherein said floating body region is formed in a substrate, said cell further comprising insulating layers bounding side surfaces of said substrate.

199. The cell of claim 193, wherein said trapping layer comprises first and second storage locations, said first and second storage locations each being configured to store data independently of the other, as non-volatile memory.

195. (canceled)

198. (canceled)

200-211. -211. (canceled)

212. A semiconductor memory cell comprising:

a substrate;

a floating body region configured to store volatile memory;

a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and

a select gate positioned adjacent said substrate and said floating gate.

213. The semiconductor memory cell of claim 212, wherein said floating body is exposed at a surface of said substrate, said cell further comprising:

first and second regions each exposed at said surface at locations other than where said floating body region is exposed;

wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

214. The semiconductor memory cell of claim 213, wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.

215. The semiconductor memory cell of claim 213, further comprising a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region.

216. The semiconductor memory cell of claim 215, wherein said floating body is bounded by said surface, said first and second regions and said buried layer.

217. The semiconductor memory cell of claim 212, further comprising insulating layers bounding side surfaces of said substrate.

218. The semiconductor memory cell of claim 213, further comprising a buried insulator layer buried in a bottom portion of said substrate.

219. The semiconductor memory cell of claim 218, wherein said floating body is bounded by said surface, said first and second regions and said buried insulator layer.

220-233. -233. (canceled)