Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
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Citations
220 Claims
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1-175. -175. (canceled)
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176. A semiconductor memory cell comprising:
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a substrate having a first conductivity type; a substrate terminal connected to said substrate; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; one of a bit line terminal and a source line terminal connected to said first region; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; the other of said bit line terminal and said source line terminal connected to said second region; a trapping layer positioned in between the first and second locations and above a surface of the substrate;
the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, wherein said first and second storage locations are each configured to receive transfer of data stored by the volatile memory; anda control gate positioned above the trapping layer. - View Dependent Claims (177, 178, 180, 183)
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179. (canceled)
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181-182. -182. (canceled)
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184-192. -192. (canceled)
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193. A semiconductor memory cell comprising:
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a floating body region for storing data as volatile memory; and a trapping layer for storing data as non-volatile memory; wherein the data stored as volatile memory and the data stored as non-volatile memory are independent of one another, as said floating body region can be operated independently of said trapping layer and said trapping layer can be operated independently of said floating body region. - View Dependent Claims (194, 196, 197, 199)
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195. (canceled)
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198. (canceled)
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200-211. -211. (canceled)
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212. A semiconductor memory cell comprising:
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a substrate; a floating body region configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and a select gate positioned adjacent said substrate and said floating gate. - View Dependent Claims (213, 214, 215, 216, 217, 218, 219)
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220-233. -233. (canceled)
Specification