POWER GATING CONTROL MODULE, INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE, AND METHOD THEREFOR

• US 20130015904A1
• Filed: 03/22/2010
• Published: 01/17/2013
• Est. Priority Date: 03/22/2010
• Status: Abandoned Application

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Priel, Michael, Rozen, Anton, Shoshany, Yossi
• Application Number:
  US13/634,716
• Publication Number:
  US 20130015904A1
• Time in Patent Office: Days
• US Class Current: 327/419
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

Claims

1. An integrated circuit device comprising:

at least one signal processing module; and

a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module

wherein the power gating control module is arranged to receive at least one operating parameter, configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter, and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

2. The integrated circuit device of claim 1 wherein the power gating control module comprises a state-retention power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module whilst a power supply to at least one state element of the at least part of the at least one signal processing module for which power is gated is maintained.

3. The integrated circuit device of claim 1, wherein the at least one operating parameter received by the power gating control module comprises at least one from a group consisting of:

an indication of an ambient temperature;

an indication of a supply voltage for at least a part of the at least one signal processing module;

an indication of a processing load for at least a part of the at least one signal processing module; and

an indication of a configurable setting.

4. The integrated circuit device of claim 3 wherein the power gating control module is arranged to receive an indication of an ambient temperature and is further arranged:

upon receipt of an indication of a low ambient temperature to configure a lower frequency power gating setting for at least part of the at least one signal processing module;

or

upon receipt of an indication of a high ambient temperature to configure a higher frequency power gating setting for at least part of the at least one signal processing module.

5. The integrated circuit device of claim 1 wherein the power gating control module is further arranged to configure a clock distribution network for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

6. The integrated circuit device of claim 1 wherein the power gating module is arranged to apply power gating in accordance with the at least one configured power gating setting for at least one from a group consisting of:

at least one signal processing core;

a memory element; and

a functional logic block.

11. The integrated circuit device of claim 2, wherein the at least one operating parameter received by the power gating control module comprises at least one from a group consisting of:

an indication of an ambient temperature;

an indication of a supply voltage for at least a part of the at least one signal processing module;

an indication of a processing load for at least a part of the at least one signal processing module; and

an indication of a configurable setting.

12. The integrated circuit device of claim 2 wherein the power gating control module is further arranged to configure a clock distribution network for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

13. The integrated circuit device of claim 3 wherein the power gating control module is further arranged to configure a clock distribution network for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

14. The integrated circuit device of claim 4 wherein the power gating control module is further arranged to configure a clock distribution network for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

15. The integrated circuit device of claim 2 wherein the power gating module is arranged to apply power gating in accordance with the at least one configured power gating setting for at least one from a group consisting of:

at least one signal processing core;

a memory element; and

a functional logic block.

16. The integrated circuit device of claim 3 wherein the power gating module is arranged to apply power gating in accordance with the at least one configured power gating setting for at least one from a group consisting of:

at least one signal processing core;

a memory element; and

a functional logic block.

17. The integrated circuit device of claim 4 wherein the power gating module is arranged to apply power gating in accordance with the at least one configured power gating setting for at least one from a group consisting of:

at least one signal processing core;

a memory element; and

a functional logic block.

18. The integrated circuit device of claim 5 wherein the power gating module is arranged to apply power gating in accordance with the at least one configured power gating setting for at least one from a group consisting of:

at least one signal processing core;

a memory element; and

a functional logic block.

7. A signal processing system comprising:

at least one signal processing module;

a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module,

wherein the power gating control module is arranged to receive at least one operating parameter, configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter, and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

8. (canceled)

9. (canceled)

10. A method for dynamically controlling gating of at least one power supply to at least a part of a signal processing module, the method comprising:

receiving at least one operating parameter;

configuring at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and

applying power gating for at least part of the signal processing module in accordance with the at least one configured power gating setting.