MEMORY DEVICE WITH TRIMMABLE POWER GATING CAPABILITIES

• US 20130016573A1
• Filed: 07/11/2011
• Published: 01/17/2013
• Est. Priority Date: 07/11/2011
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Goel, Ankur, Konudula, Venkateswara Reddy, Gowda, Sathisha Nanjunde
• Granted Patent: US 8,427,886 B2
• Time in Patent Office: Days
• US Class Current: 365/189.06
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Claims

1. A memory device, comprising:

at least one memory cell including a storage element electrically connected with a source potential line, a drive strength of the storage element being controlled as a function of a voltage level on the source potential line;

a clamp circuit electrically connected between the source potential line and a voltage source, the clamp circuit being operative to regulate the voltage level on the source potential line relative to the voltage source; and

a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.

2. The memory device of claim 1, wherein the control circuit is operative to electrically connect the source potential line to the voltage source when the memory cell is in a first mode of operation, and to electrically disconnect the source potential line from the voltage source when the memory cell is in a second mode of operation.

3. The memory device of claim 2, wherein the control circuit is operative to set the source potential line at a first potential while the memory cell is in the first mode, and to set the source potential line at a second potential while the memory cell is in the second mode.

4. The memory device of claim 3, wherein the second potential is higher than the first potential.

5. The memory device of claim 2, wherein the first mode is a memory access mode of the memory device and the second mode is a standby mode of the memory device.

6. The memory device of claim 2, wherein the control circuit is operative to set the source potential line at a plurality of different potentials while the memory cell is in the second mode.

7. The memory device of claim 2, wherein the control circuit is operative to set the source potential line at four or more different potentials while the memory cell is in the second mode.

8. The memory device of claim 1, wherein the control circuit comprises a trimming circuit electrically connected between the source potential line and the voltage source, the trimming circuit comprising one or more first trimming transistors that are selectively activated by at least the first control signal.

9. The memory device of claim 1, wherein the clamp circuit comprises at least one MISFET connected in a diode configuration between the source potential line and the voltage source.

10. The memory device of claim 1, wherein the at least one memory cell is of a static type.

11. The memory device of claim 1, wherein the storage element in the at least one memory cell comprises two cross-coupled inverters forming a latch.

12. The memory device of claim 11, wherein each of the cross-coupled inverters comprises a MISFET having a source connected with the source potential line.

13. The memory device of claim 1, wherein the voltage source is fixed at a ground potential for the memory device.

14. The memory device of claim 1, wherein the coarseness by which the voltage level on the source potential line is adjusted is selectively controlled by the control circuit as a function of a plurality of digital control signals.

15. The memory device of claim 1, wherein the at least one control signal comprises a plurality of control signals, and wherein the control circuit comprises a trimming circuit including a plurality of variable resistance paths electrically connected between the source potential line and the voltage source, each of the variable resistance paths comprising at least one transistor activated by a given one of the plurality of control signals.

16. The memory device of claim 15, wherein at least a given one of the transistors in the trimming circuit is configured having a weak inversion region when the given transistor is turned on.

17. The memory device of claim 1, wherein the trimming circuit comprises:

a first variable resistance path including one or more first trimming transistors activated by the first control signal and connected together in series between the source potential line and the voltage source; and

at least a second variable resistance path including one or more second trimming transistors activated by a second control signal, at least one of the second trimming transistors being connected in parallel with at least one of the first trimming transistors.

18. The memory device of claim 17, wherein the memory device is operative to separately assert the first and second control signals.

19. The memory device of claim 17, wherein the trimming circuit comprises at least a third variable resistance path including one or more third trimming transistors activated by a third control signal, at least one of the third trimming transistors being connected in parallel with at least one of:

(i) at least one of the first trimming transistors; and

(ii) at least one of the second trimming transistors.

20. The memory device of claim 19, wherein the memory device is operative to separately assert the first, second and third control signals.

21. A power gating circuit for use with a memory device having at least one memory cell including a storage element electrically connected with a source potential line, the power gating circuit comprising:

a clamp circuit electrically connected between the source potential line and a voltage source of the memory device, the clamp circuit being operative to regulate a voltage level on the source potential line relative to the voltage source; and

a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.

22. An electronic system, comprising:

at least one integrated circuit, the at least one integrated circuit including at least one power gating circuit for use with a memory device having at least one memory cell including a storage element electrically connected with a source potential line, the at least one power gating circuit comprising;

a clamp circuit electrically connected between the source potential line and a voltage source of the memory device, the clamp circuit being operative to regulate a voltage level on the source potential line relative to the voltage source; and

a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.

23. An integrated circuit comprising at least one memory device, the at least one memory device comprising:

at least one memory cell including a storage element electrically connected with a source potential line, a drive strength of the storage element being controlled as a function of a voltage level on the source potential line;

a clamp circuit electrically connected between the source potential line and a voltage source, the clamp circuit being operative to regulate the voltage level on the source potential line relative to the voltage source; and

a control circuit connected with the source potential line, the control circuit being operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device, a coarseness by which the voltage level on the source potential line is adjusted being selectively controlled by the control circuit as a function of at least a first control signal.

24. The integrated circuit of claim 23, wherein the at least one memory device comprises a static random access memory.