SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS

• US 20130016574A1
• Filed: 07/13/2012
• Published: 01/17/2013
• Est. Priority Date: 07/15/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jung-sik, Kim, Cheol, Choi, Joo-sun, Shin, Sang-ho, Lee, Jung-bae, Lee, Chan-yong, Yim, Sung-min, Jang, Tae-seong
• Granted Patent: US 9,036,439 B2
• Time in Patent Office: Days
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Claims

1. A semiconductor memory device comprising:

a memory array including a plurality of memory cells;

a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal;

a storage unit configured to store the first fail address signal; and

a refresh unit configured to perform a refresh operation on the memory array, the refresh unit being configured to receive the first fail address signal from the storage unit, refresh a first memory cell that does not correspond to the first fail address signal according a first period, and refresh a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

2. The semiconductor memory device of claim 1, wherein the test unit is configured to perform the refresh operation on the memory array, determine whether the memory array retains data after a time period elapses, and store a row address signal corresponding to a memory cell that does not retain the data in the storage unit as the first fail address signal.

3. The semiconductor memory device of claim 1, wherein the refresh unit comprises:

a comparator configured to compare the first fail address signal with a first address signal corresponding to the first memory cell and the first fail address signal with a second address signal corresponding to the second memory cell, and generate a comparison signal; and

a period controller configured to generate a period setting signal according to the comparison signal and transmit the period setting signal to the memory array.

4. The semiconductor memory device of claim 1, further comprising:

a mode register configured to store a test mode code, wherein the test unit is configured to activate in response to the test mode code stored in the mode register.

5. The semiconductor memory device of claim 1, wherein the first period is a multiple of the second period.

6. The semiconductor memory device of claim 1, wherein the storage unit includes an electrical fuse.

7. The semiconductor memory device of claim 1, wherein

the memory array includes a first memory block including the first memory cell, and a second memory block including the second memory cell, and

the refresh unit is configured to refresh the first memory block according to the first period and refresh the second memory block according to the second period.

8. The semiconductor memory device of claim 1, wherein

the memory array includes a first bank and a second bank, each of the first bank and the second bank including a first memory cell and a second memory cell,

while the second bank is activated, the first bank is inactivated, and

the refresh unit is configured to refresh the first memory cell and the second memory cell of the first bank that is inactivated.

9. The semiconductor memory device of claim 1, wherein

the test unit is configured to test the refresh characteristics of the plurality of memory cells and generate a second fail address signal,

the storage unit is configured to store the second fail address signal, and

the refresh unit is configured to refresh a third memory cell corresponding to the second fail address signal according to a third period that is shorter than the second period.

10. A system comprising:

the semiconductor memory device of claim 1; and

an external device configured to issue a command, the command activating the test unit included in the semiconductor memory device.

11. The system of claim 10, wherein the semiconductor memory device further comprises:

a mode register configured to store a test mode code, wherein, if the external device transmits the test mode code to the mode register and the test mode code is stored in the mode register, the test unit is configured to activate in response to the test mode code stored in the mode register.

12. A semiconductor memory device comprising:

a memory array including a first memory cell and a second memory cell;

a storage unit configured to store as a fail address signal a second address signal corresponding to the second memory cell; and

a refresh unit configured to perform a refresh operation on the memory array, the refresh unit being configured to receive the fail address signal from the storage unit, not refresh the first memory cell and refresh the second memory cell in a first time section of the refresh operation, and the refresh unit being configured to refresh both the first memory cell and the second memory cell in a second time section of the refresh operation.

13. The semiconductor memory device of claim 12, wherein the refresh unit is configured to refresh the second memory cell according to a second period corresponding to a time difference between the first time section and the second time section, and refresh the first memory cell according to a first period that is longer than the second period.

14. The semiconductor memory device of claim 12, further comprising:

a built in self-test (BIST) unit configured to test refresh characteristics of the memory array, generate the fail address signal, and store the fail address signal in the storage unit.

15. A system comprising:

the semiconductor memory device of claim 12; and

a memory control unit configured to control the semiconductor memory device, the memory control unit being configured to test refresh characteristics of the memory array included in the semiconductor memory device, generate the fail address signal, and store the fail address signal in the storage unit.

16. A semiconductor memory device comprising:

a memory cell;

a test unit configured to test refresh characteristics of the memory cell to determine whether the memory cell is a good cell or a bad cell;

a storage unit configured to store a row address of the memory cell if the memory cell is a bad cell; and

a refresh unit configured to perform a refresh operation on the memory cell according to a refresh period, the refresh period being based on whether the memory cell is a good cell or a bad cell.

17. The device of claim 16, wherein the refresh period is a first period if the memory cell is a good cell and the refresh period is a second period if the memory cell is a bad cell, and the second period is shorter than the first period.

18. The device of claim 16, wherein the refresh operation includes first, second, and third time sections, and the refresh unit is configured to refresh a good cell at the first and third time sections and refresh a bad cell at the first, second, and third time sections.

19. The device of claim 16, wherein the memory cell is one of a plurality of memory cells in a memory array, and the refresh unit is configured to refresh each memory cell in the memory array according to the refresh period.

20. The device of claim 16, wherein the refresh unit includes:

a comparator configured to generate a comparison signal based on the stored row address of the memory cell and a refresh address, the comparison signal indicating whether the refresh address corresponds to a good cell or a bad cell; and

a period controller configured to generate a period setting signal indicating the refresh period based on the comparison signal.