Methods for Coordinated Signal Reception Across Integrated Circuit Boundaries
First Claim
1. A wireless electronic device comprising:
- at least one antenna;
a first baseband processor integrated circuit coupled to the antenna, wherein the first baseband processor integrated circuit is operable in a first baseband processor sleep state from which the first baseband processor integrated circuit awakes for a first wake period; and
a second baseband processor integrated circuit coupled to the antenna, wherein the second baseband processor integrated circuit is operable in a second baseband processor sleep state from which the second baseband processor integrated circuit awakes for a second wake period and is operable to send control signals to the first baseband processor integrated circuit to avoid collisions between the first and second wake periods.
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Abstract
A wireless electronic device having first and second baseband processors is provided. In one suitable arrangement, radio-frequency power splitters and adjustable low noise amplifiers may be form in the receive paths. The use of power splitters allow signals associated with the first and second baseband processors to be received in parallel. In another suitable arrangement, radio-frequency switches are used in place of the power splitters. The states of the switches may be controlled using at least one of the first and second baseband processors. The use of switches instead of power splitters requires that wake periods associated with the first baseband processor and wake periods associated with the second baseband processor are non-overlapping. To ensure minimal wake period collision, a wake period associated with the second baseband processor may be positioned at a midpoint between two successive wake periods associated with the first baseband processor.
36 Citations
20 Claims
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1. A wireless electronic device comprising:
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at least one antenna; a first baseband processor integrated circuit coupled to the antenna, wherein the first baseband processor integrated circuit is operable in a first baseband processor sleep state from which the first baseband processor integrated circuit awakes for a first wake period; and a second baseband processor integrated circuit coupled to the antenna, wherein the second baseband processor integrated circuit is operable in a second baseband processor sleep state from which the second baseband processor integrated circuit awakes for a second wake period and is operable to send control signals to the first baseband processor integrated circuit to avoid collisions between the first and second wake periods. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for operating an electronic device with first and second baseband processor integrated circuits with sleep states from which each integrated circuit awakens, the method comprising:
conveying information between the first and second baseband processor integrated circuits using inter-processor communications to avoid wakeup time collisions between the first and second baseband processor integrated circuits. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A wireless electronic device comprising:
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at least one antenna; a first baseband processor integrated circuit coupled to the antenna; a second baseband processor integrated circuit coupled to the antenna; a first radio-frequency power splitter coupled between the first baseband processor integrated circuit and the antenna; and a second radio-frequency power splitter coupled between the second baseband processor integrated circuit and the antenna. - View Dependent Claims (17, 18, 19, 20)
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Specification