METHOD OF IMPROVING REPLACEMENT METAL GATE FILL

• US 20130017680A1
• Filed: 07/14/2011
• Published: 01/17/2013
• Est. Priority Date: 07/14/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Haran, Balasubramanian S., Demarest, James J.
• Granted Patent: US 8,629,007 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of making a gate of a field effect transistor (FET) with improved fill by a replacement gate process using a sacrificial film includes providing a substrate with a dummy gate. It further includes depositing a sacrificial layer and an encapsulating layer over the substrate, and planarizing so that the encapsulating layer, sacrificial layer and dummy gate are co-planar. The encapsulating layer and a portion of the sacrificial film are removed to leave a remaining sacrificial film. The dummy gate is removed to form and opening in the remaining sacrificial film and to expose sidewalls of the film. Spacers are formed on the sidewalls. A high dielectric constant film and metal film are deposited in the opening and planarized to form a gate. The remaining sacrificial film is removed. The method can be used on planar FETs as well non-planar FETs.

Claims

1. A method of forming a gate of a field effect transistor (FET), the method comprising:

forming a dummy gate, and sacrificial layer above a substrate;

exposing a portion of the dummy gate;

removing the dummy gate and a portion of the sacrificial layer to leave a remaining portion of the sacrificial layer on the substrate;

depositing a high dielectric constant (high-k) film and depositing a metal film on the high-k film;

planarizing the substrate wherein the metal film, the high-k film, and the remaining sacrificial layer are co-planar; and

removing the remaining portion of the sacrificial layer.

2. The method of claim 1, wherein removing the dummy gate and a portion of the sacrificial layer creates a dummy gate opening.

3. The method of claim 2, further comprises forming a spacer adjacent to the dummy gate opening and wherein forming the spacer modifies the dummy gate opening resulting in a spacer opening having a aspect ratio of 2.5:

1.

4. The method of claim 1, further comprising a void-free gate.

5. The method of claim 1, wherein said forming the sacrificial layer creates a conformal and non-uniform sacrificial layer.

6. The method of claim 5, wherein said sacrificial layer has a first thickness on a horizontal plane and a second thickness on a vertical plane, said first thickness being greater than said second thickness.

7. The method of claim 1, wherein the FET is a planar FET.

8. The method of claim 1, wherein the FET is a non-planar FET.

9. A method of fabricating a gate in a Field Effect Transistor (FET), comprising:

providing a substrate with an isolation area, an active area and a step height between the isolation area and the active area;

forming at least one dummy gate above the isolation area and forming at least one dummy gate above the active area;

depositing a sacrificial layer;

exposing a portion of the dummy gates;

removing the dummy gates, and a portion of the sacrificial layer leaving a remaining portion of the sacrificial layer to create a dummy gate opening above the isolation area and a dummy gate opening above the active area;

depositing a high dielectric constant (high-k) film and depositing a metal film on the high-k film;

planarizing the substrate wherein the metal film, the high-k film, and the remaining portion of the sacrificial layer are co-planar to form a first gate over the isolation area and a second gate over the active area; and

removing the remaining portion of the sacrificial layer.

10. The method of claim 9, further comprising forming a spacer adjacent each of the dummy gate openings wherein forming the spacer modifies each of the dummy gate openings resulting in a first spacer opening over the isolation area having a first spacer opening aspect ratio and a second spacer opening over the active area having a second spacer opening aspect ratio.

11. The method of claim 10, wherein the first spacer opening aspect ratio equals the second spacer opening aspect ratio.

12. The method of claim 9, wherein said planarizing to form the first and second gates results in a void-free second gate.

13. The method of claim 9, wherein said planarizing to form the first and second gates results in a first gate height of the first gate and a second gate height of the second gate;

wherein the first gate height exceeds the step height.

14. The method of claim 9, wherein said planarizing to form the first and second gates results in a first aspect ratio of the first gate and a second aspect ratio of the second gate;

wherein the second aspect ratio is less than 2.5;

1.

15. The method of claim 14, wherein the first aspect ratio of the first gate is greater than the second aspect ratio of the second gate.

16. The method of claim 9, wherein said planarizing to form the first and second gates results in a first gate height of the first gate and a second gate height of the second gate;

wherein the first gate height is different than the second gate height.

17. The method of claim 16, wherein the first gate height is greater than the second gate height.

18. The method of claim 9, wherein the FET is a planar FET.

19. The method of claim 9, wherein the FET is a non-planar FET.

20. A method of making a reduced aspect ratio opening in a replacement gate process of making a Field Effect Transistor (FET), the method comprising:

providing a substrate with a dummy gate;

depositing a sacrificial layer having a first thickness on a horizontal surface of the substrate and on a horizontal surface of the dummy gate, and a second thickness on a sidewall of the dummy gate;

exposing a portion of the dummy gate by removing the first thickness of the sacrificial layer on the horizontal surface of the dummy gate; and

removing the second thickness of the sacrificial layer and the dummy gate to leave a remaining portion of the sacrificial layer on the substrate.