FLASH CONTROLLER HARDWARE ARCHITECTURE FOR FLASH DEVICES

• US 20130019053A1
• Filed: 03/28/2012
• Published: 01/17/2013
• Est. Priority Date: 07/14/2011
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Swatosh, Timothy W., Ellis, Jackson L., Hicken, Michael S., Dell, Martin S., Somanache, Vinay Ashok, Hempstead, Pamela S.
• Application Number:
  US13/432,394
• Publication Number:
  US 20130019053A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A flash media controller including one or more dedicated data transfer paths, one or more flash lane controllers, and one or more flash bus controllers. The one or more flash lane controllers are generally coupled to the one or more dedicated data transfer paths. The one or more flash bus controllers are generally coupled to the one or more flash lane controllers.

Claims

1. A flash media controller comprising:

one or more dedicated data transfer paths;

one or more flash lane controllers coupled to said one or more dedicated data transfer paths; and

one or more flash bus controllers coupled to said one or more flash lane controllers.

2. The flash media controller according to claim 1, wherein said flash media controller implements a context containing information needed to perform a transaction with a flash bank.

3. The flash media controller according to claim 2, wherein said flash media controller implements independent linked lists of contexts per logical unit in said flash bank.

4. The flash media controller according to claim 1, wherein said flash media controller is configured to fetch contexts from multiple context links.

5. The flash media controller according to claim 1, further comprising a consumed context manager configured to provide a single interface where all completed status from all logical units associated with said flash media controller are reported.

6. The flash media controller according to claim 1, wherein said one or more flash lane controllers each comprise a die-management table holding a current status of fetched contexts for each die attached to said flash lane controllers and a context manager configured to manage execution of contexts by said flash media controller.

7. The flash media controller according to claim 1, wherein full duplex operation is supported in each of the one or more flash lane controllers.

8. The flash media controller according to claim 1, wherein said flash media controller implements a plurality of flash lanes, each flash lane having an independent lane architecture including a respective one of said dedicated data transfer paths.

9. An apparatus comprising:

at least two dedicated data transfer paths;

at least two flash lane controllers coupled to said at least two dedicated data transfer paths; and

at least two flash bus controllers coupled to said at least two flash lane controllers.

10. The apparatus according to claim 9, further comprising a plurality of flash storage devices arranged as at least two independent lanes.

11. The apparatus according to claim 10, wherein said apparatus comprises a system on a chip.

12. The apparatus according to claim 9, wherein each flash transaction is represented by a context.

13. The apparatus according to claim 12, wherein said context comprises a data structure containing all information needed by said apparatus to either perform a transaction with a flash bank or move data to or from a location in a system buffer.

14. The apparatus according to claim 13, wherein said data structure is further configured to provide a linked list of contexts for each flash unit attached to said apparatus.