SILICIDED DEVICE WITH SHALLOW IMPURITY REGIONS AT INTERFACE BETWEEN SILICIDE AND STRESSED LINER
First Claim
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1. A method of forming a semiconductor device, the method comprising:
- forming a silicide contact region of a field effect transistor (FET);
forming a shallow impurity region in a top surface of the silicide contact region; and
forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
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Abstract
A method of forming a semiconductor device includes forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region.
11 Citations
20 Claims
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1. A method of forming a semiconductor device, the method comprising:
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forming a silicide contact region of a field effect transistor (FET); forming a shallow impurity region in a top surface of the silicide contact region; and forming a stressed liner over the FET such that the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A field effect transistor (FET), comprising:
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a gate structure formed over a substrate; source and drain regions formed in the substrate, adjacent the gate structure silicide contact regions formed on the gate structure, source and drain regions, the silicide contacts having a shallow impurity region located at a top surface thereof; and a stressed liner formed over the FET, wherein the shallow impurity region is located at an interface between the silicide contact region and the stressed liner, and wherein the shallow impurity region comprises one or more impurities, and is configured to hinder diffusion of silicon within the silicide contact region and prevent morphological degradation of the silicide contact region. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification