Intelligent Battery With Off-Line Spare Battery Charging and Output Regulation System

• US 20130020998A1
• Filed: 07/23/2012
• Published: 01/24/2013
• Est. Priority Date: 07/21/2011
• Status: Abandoned Application

• Current Assignee: Levitate IP LLC
• Original Assignee: Levitate IP LLC
• Inventors: Howard, Ryan Robert
• Application Number:
  US13/556,190
• Publication Number:
  US 20130020998A1
• Time in Patent Office: Days
• US Class Current: 320/117
• CPC Class Codes: H02J 1/001 Hot plugging or unplugging of load or power modules to or from power distribution networks
• CPC Class Codes: H02J 7/0013 acting upon several batteries simultaneously or sequentially H02J7/1423 takes precedence
• CPC Class Codes: H02J 7/0029 with safety or protection devices or circuits
• CPC Class Codes: H02J 7/00304 Overcurrent protection
• CPC Class Codes: H02J 7/00308 Overvoltage protection

Abstract

A battery pack having multiple cells connected through “virtual” connections via MOSFETs, other insulated-gate field-effect transistors, and the like. The use of virtual connections allows for the use of one or more “spare” battery cells, which may be swapped in for underperforming cells or to take discharged cells offline for charging. A microprocessor monitors and manages individual battery cells or batteries in an array. The battery pack of the present disclosure may further include an optional cooling system and/or a novel encapsulation to protect the cells and electronics from use in harsh environments.

Claims

1. An intelligent battery system comprising:

a plurality of battery cells, wherein each battery cell is connected to another battery cell by at least one TMOS junction, and wherein each TMOS junction comprises at least three insulated-gate field-effect transistors joined at a respective source node of each insulated-gate field-effect transistor; and

a microprocessor in electrical communication with the at least one TMOS junction.

2. The intelligent battery system of claim 1, further comprising a USB version detection module.

3. The intelligent battery system of claim 1, further comprising an array of battery packs, wherein:

each battery pack comprises a plurality of battery cells and

a first battery pack is in electrical communication with a second battery pack, wherein the first and second battery packs are within the array of battery packs.

6. The intelligent battery system of claim 1, further comprising a temperature sensor adapted to measure a temperature of a selected battery cell and transmit said temperature to the microprocessor.

7. The intelligent battery system of claim 1, wherein the at least one TMOS junction is adapted to selectively remove a battery cell from electrical communication with a battery terminal.

8. The intelligent battery system of claim 1, wherein the plurality of battery cells and the at least one TMOS junction are encapsulated in an encapsulant.

9. The intelligent battery system of claim 8, wherein the encapsulant comprises an epoxy.

10. The intelligent battery system of claim 1, wherein the plurality of battery cells comprises a spare battery cell.

11. The intelligent battery system of claim 1, further comprising a Peltier device.

12. The intelligent battery system of claim 11, wherein the Peltier device, the plurality of battery cells, and the at least one TMOS junction are encapsulated in an encapsulant.

13. The intelligent battery system of claim 1, wherein the at least one TMOS junction is adapted to electrically place at least some of the plurality of battery cells in series.

14. The intelligent battery system of claim 1, wherein the at least one TMOS junction is adapted to electrically place at least some of the plurality of battery cells in parallel.

4. A method of maintaining a battery pack, comprising:

monitoring one or more conditions of a plurality of cells in the battery pack, the one or more conditions selected from the group consisting of voltage output, current output, output duration, recharge time, temperature, charge rate, voltage drop point, and current drop point;

identifying an underperforming cell;

placing a spare cell into electrical communication with a battery terminal; and

removing the underperforming cell from electrical communication with the battery terminal.

5. The method of claim 4, wherein the underperforming cell comprises a discharged cell, the method further, comprising:

recharging the discharged cell, thereby resulting in a charged cell;

placing the charged cell into electrical communication with the battery terminal; and

removing the spare cell from electrical communication with the battery terminal.

15. The method of claim 4, wherein:

placing the spare cell into electrical communication with the battery terminal and

removing the underperforming cell from electrical communication with the battery terminal

are performed by at least one TMOS junction;

wherein the at least one TMOS junction comprises at least three insulated-gate field-effect transistors joined at a respective source node of each insulated-gate field-effect transistor.

16. The method of claim 4, further comprising selectively applying heat to the battery pack in response to a temperature below a preselected threshold.

17. The method of claim 4, further comprising selectively cooling the battery pack in response to a temperature above a preselected threshold.

18. The method of claim 5, wherein:

placing the charged cell into electrical communication with the battery terminal and

removing the spare cell from electrical communication with the battery terminal

are performed by at least one TMOS junction;

wherein the at least one TMOS junction comprises at least three insulated-gate field-effect transistors joined at a respective source node of each insulated-gate field-effect transistor.

19. The method of claim 5, wherein recharging the discharged cell comprises regulating a recharge voltage via pulse width modulation.

20. A method of providing electrical power, comprising:

electrically placing a plurality of battery cells in parallel via at least one TMOS junction;

wherein the at least one TMOS junction comprises at least three insulated-gate field-effect transistors joined at a respective source node of each insulated-gate field-effect transistor; and

in response to a changed power need, electrically placing the plurality of battery cells in series via the at least one TMOS junction.