3D VIDEO PROCESSING UNIT

• US 20130021438A1
• Filed: 03/30/2011
• Published: 01/24/2013
• Est. Priority Date: 03/31/2010
• Status: Abandoned Application

• Current Assignee: Design Flux Technologies, LLC
• Original Assignee: Design Flux Technologies, LLC
• Inventors: Tucker, Lawrence J.
• Application Number:
  US13/637,822
• Publication Number:
  US 20130021438A1
• Time in Patent Office: Days
• US Class Current: 348/43
• CPC Class Codes: H04N 13/161 Encoding, multiplexing or demultiplexing different image signal components for multi-view video sequence encoding H04N19/597
• CPC Class Codes: H04N 13/178 Metadata, e.g. disparity information
• CPC Class Codes: H04N 13/302 for viewing without the aid of special glasses, i.e. using autostereoscopic displays
• CPC Class Codes: H04N 13/398 Synchronisation thereof; Control thereof

Abstract

The 3D video processing unit combines video feeds from two unsynchronized video sources, such as left and right video cameras, in real-time, to generate a 3D image for display on a video monitor. The processing unit can also optionally receive video data from a third video source and use that data to generate a background image visible on all or a selected portion or portions of the video monitor. An alpha data generator inspects the video data held within respective buffer circuits associated with the left and right channels and generates an alpha data value for each pixel. These alpha data values are used within an alpha blending mixer to control whether a pixel is displayed or suppressed. Synchronization of the unsynchronized video sources occurs within the processing unit after alpha data values have been generated for each left and right channels.

Claims

1. A 3D video processing apparatus comprising:

first input processing block receptive of video information from a first source and producing first video data;

first frame buffer coupled to said first input that receives, organizes and stores said first video data as buffered first video data defining at least one frame comprising a plurality of pixels;

first alpha data generator coupled to said first frame buffer and operative to inspect said buffered first video data on a pixel-by-pixel basis to generate and associate with each pixel an alpha data value;

second input processing block receptive of video information from a second source and producing second video data;

second frame buffer coupled to said first input that receives, organizes and stores said second video data as buffered second video data defining at least one frame comprising a plurality of pixels;

second alpha data generator coupled to said first frame buffer and operative to inspect said buffered second video data on a pixel-by-pixel basis to generate and associate with each pixel an alpha data value;

an alpha blending mixer receptive of said buffered first and second video data and the alpha data values associated therewith and operative to combine said first and second buffered video data into a single video output data according to the alpha data values;

a video output processing block coupled to said alpha blending mixer and supplying said output data as a clocked video output for display on a monitor.

2. The apparatus of claim 1 wherein each of said first and second alpha data generators includes a mode select control port and the apparatus further comprises a processor that supplies mode select information to said control ports.

3. The apparatus of claim 1 wherein said first and second alpha data generators each comprise a decoder logic circuit that extracts information from the first and second video data respectively and a data generation circuit that generates alpha data values based on the extracted information.

4. The apparatus of claim 3 wherein the data generation circuit generates alpha data values based on the extracted information and on a user-specified operating mode.

5. The apparatus of claim 4 wherein said user-specified operating mode is supplied to the data generation circuit by a mode select processor.

6. The apparatus of claim 1 wherein the first and second input processing blocks define the first and second frame-based video data as packetized data having header and data fields.

7. The apparatus of claim 1 wherein said first and second input processing blocks define the first and second frame-based video data as packetized data by extracting video and synchronization data from the video information received from the first and second sources respectively.

8. The apparatus of claim 1 further comprising first camera serving as said first source and a second camera serving as said second source, and wherein the first and second camera are unsynchronized with respect to each other.

9. The apparatus of claim 1 further comprising first camera serving as said first source and a second camera serving as said second source, each of said cameras having a clocking circuit that measures time independently of another clocking circuit.

10. The apparatus of claim 1 wherein the alpha blending mixer is configured to pull buffered video data from the first and second frame buffers when each contains a start-of-frame indicia and to thereby synchronize the first and second buffered video data for processing as a single blended video data frame.

11. The apparatus of claim 1 further comprising additional video data source coupled to said alpha blending mixer and wherein the alpha blending mixer is configured to blend additional video data with said first and second buffered video data to compose the single video output data.

12. The apparatus of claim 1 wherein the first and second alpha data generators selectively generate one of a plurality of different predefined 3D encoding formats selected from the group consisting of:

a first format in which alternating rows of pixels are suppressed;

a second format in which alternating columns of pixels are suppressed;

a third format in which a checkerboard matrix of pixels are suppressed;

a fourth format in which a contiguous region of pixels are suppressed.