NONVOLATILE MEMORY AND METHOD OF CONTROLLING THEREOF

• US 20130021852A1
• Filed: 07/19/2012
• Published: 01/24/2013
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, JAEYONG
• Granted Patent: US 8,705,294 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.

Claims

1. A memory system comprising:

a nonvolatile memory including a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system; and

a controller configured to control a sensing operation of the nonvolatile memory,

wherein an operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and

wherein the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.

2. The memory system of claim 1, wherein the nonvolatile memory further includes a data detector configured to detect whether the reference data stored in the second latch unit is changed.

3. The memory system of claim 2, wherein the reference data stored in the memory cell array has a predetermined data pattern, and

wherein the data detector includes a combination logic configured to output the same data as the predetermined data pattern, and a comparator configured to compare an output of the combination logic with the reference data stored in the second latch unit.

4. The memory system of claim 1, wherein the nonvolatile memory detects whether the reference data stored in the second latch unit is changed and provides information indicative of a result of the detection to the controller.

5. The memory system of claim 4, wherein the controller transmits a reset signal to the nonvolatile memory when the result of the detection indicates the change of the reference data, and

wherein the nonvolatile memory re-stores the setup data stored in the memory cell array in the first latch unit in response to the reset signal.

6. The memory system of claim 4, wherein the controller generates a latch status read signal when the voltage level of a power supply is lower than a critical voltage level, and

wherein the nonvolatile memory provides information indicative of the result of the detection to the controller in response to the latch status read signal.

7. The memory system of claim 1, wherein the nonvolatile memory further includes:

a status register configured to store first and second status bits;

a control logic configured to set up the first status bit depending on whether the sensing operation is performed; and

a data detector configured to detect whether the reference data stored in the second latch unit is changed and set up the second status bit according to a result of the detection.

8. The memory system of claim 7, wherein the controller generates a latch status read signal at the power-up or when the voltage level of the power is lower than a critical voltage level,

wherein the nonvolatile memory provides the first and second status bits to the controller in response to the latch status read signal, and

wherein the controller transmits an initialization signal to the nonvolatile memory according to a value of the first status bit and transmits a reset signal to the nonvolatile memory according to a value of the second status bit.

9. The memory system of claim 8, wherein the nonvolatile memory initializes the first latch unit according to the initialization signal and re-stores the reference data in the first latch unit from the memory cell array according to the reset signal.

10. A memory device comprising:

a nonvolatile memory array configured to store setup data and reference data;

a read circuit connected to the nonvolatile memory array;

a latch circuit connected to the read circuit;

a control logic configured to load the setup data and the reference data into the latch circuit via the read circuit upon a power-up of the memory device;

a data detector configured to detect a corruption of the reference data loaded into the latch circuit,

wherein the control logic is further configured to re-load the setup data and the reference data into the latch circuit when the data detector detects the corruption of the reference data.

11. The memory device of claim 10, further comprising a voltage level detector which detects a power supply voltage of the memory device, wherein the control logic is further configured to automatically read an output of the data detector when the voltage level detector indicates that the power supply voltage is less than a given voltage level.

12. The memory device of claim 10, wherein the control logic is further configured to read an output of the data detector in response to a signal received from an external controller.

13. The memory device of claim 10, wherein the data detector comprises:

a combination logic circuit configured to generate a duplicate of the reference data as stored in the memory cell array; and

a comparator for comparing the reference data loaded into the latch circuit with the generated duplicate of the reference data.

14. The memory device of claim 10, further comprising a status register including at least one first bit indicative of loading of the set-up data and reference data into the latch circuit, and at least one second bit indicative of whether the data detector has detected the corruption of the reference data loaded into the latch circuit.

15. A control method of a nonvolatile memory including a plurality of memory cells, the control method comprising:

controlling the nonvolatile memory to sense reference data and setup data stored in the memory cells at a power-up of the nonvolatile memory;

determining whether the sensed reference data is changed when a voltage level of a power becomes lower than a critical voltage level; and

controlling the nonvolatile memory to re-sense the setup data according to a result of the determination,

wherein an operating environment of the nonvolatile memory is determined according to the sensed setup data.

16. The control method of claim 15, wherein the reference data stored in the memory cells has a predetermined data pattern.

17. The control method of claim 15, wherein the sensed reference data and the sensed setup data vary with a change in voltage level of the power.

18. The control method of claim 15, wherein determining whether the sensed reference data is changed comprises:

transmitting a status read control signal to the nonvolatile memory when the voltage level of the power becomes lower than the critical voltage level; and

receiving information indicative of whether the sensed reference data is changed,

wherein the information indicative of whether the sensed reference data is provided from the nonvolatile memory in response to the status read control signal.

19. The control method of claim 15, wherein the nonvolatile memory performs an initialization operation when the power is recovered after power-down.

20. The control method of claim 19, further comprising:

checking whether the initialization operation is performed when the voltage level of the power becomes lower than the critical voltage level; and

controlling the nonvolatile memory to perform the initialization operation according to a result of the checking.